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1. 发明授权

US06603777B1 Method and apparatus for establishing frame synchronization 有权
标题翻译：用于建立帧同步的方法和装置
公开(公告)号：US06603777B1
公开(公告)日：2003-08-05
申请号：US09310103
申请日：1999-05-12
申请人： Atsuhiro Kubota
发明人： Atsuhiro Kubota
IPC分类号： H04J306
CPC分类号： H04J3/0608
摘要： The present invention provides a frame synchronous circuit wherein the number of devices handling a high-speed digital signal is limited to the minimum without deteriorating frame pull-in time and an erroneous synchronization rate. For the sake of it, synchronous word decision devices decide frame synchronization from four lines of low-speed digital signals into which the high-speed digital signal is converted by a serial-parallel converter. An OR circuit synthesizes respective outputs of the synchronous word decision devices, and an aperture circuit applies an aperture to the output synthesized. A selection circuit fetches only one output corresponding to the change of the apparent synchronous word after establishment of synchronization. A frame counter circuit estimates a predetermined position of the next frame at the time of applying a narrow aperture. A leading-edge positioning/column change circuit performs leading-edge positioning and column change of data to the output of the selection circuit.
摘要翻译：本发明提供了一种帧同步电路，其中处理高速数字信号的设备的数量被限制到最小，而不会降低帧引入时间和错误的同步速率。为此，同步字决策装置决定了由串行并行转换器转换高速数字信号的四行低速数字信号的帧同步。 OR电路合成同步字决定装置的各个输出，并且孔径电路对合成的输出施加孔径。选择电路仅在建立同步之后仅获取对应于表观同步字的变化的一个输出。帧计数器电路估计在施加窄光圈时下一帧的预定位置。前沿定位/列更改电路执行前沿定位和数据列更改到选择电路的输出。

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