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1. 发明授权

US06813282B1 Isochronous packet transfer method, computer readable recording media recorded with control program for executing isochronous packet transfer, and bridge and packet transfer control LSI 有权
标题翻译：记录有用于执行同步分组传送的控制程序的计算机可读记录介质以及桥和分组传送控制LSI的同步分组传送方法
公开(公告)号：US06813282B1
公开(公告)日：2004-11-02
申请号：US09665262
申请日：2000-09-19
申请人： Wataru Domon
发明人： Wataru Domon
IPC分类号： H04J306
CPC分类号： H04L12/40058 , H04L12/40065 , H04L12/40091 , H04L12/6418 , H04L2012/6435 , H04L2012/6456
摘要： An isochronous packet transfer method is provided which can reduce a transmit buffer size required for isochronous packet transfer, and which can give a constant delay to an isochronous packet even if transmission of a cycle start packet is delayed. An isochronous packet received from an input side bus is input to a delay section, and this isochronous packet is delayed in accordance with delay information and is transmitted to an output side bus. Input side and output side cycle identification information generating sections respectively output cycle identification information which changes at a timing at which a cycle start packet is sent to the input side bus and the output side bus. Input side and output side reference cycle identification information generating sections sample the input side and output side cycle identification information at predetermined timing and output input side and output side reference cycle identification information. A delay information generating section adds a fixed delay to a difference in the elapsed cycle number for each bus from the predetermined timing, based on input side and output side cycle identification information and input side and output side reference cycle identification information to generate delay information.
摘要翻译：提供了同步分组传送方法，其可以减少等时分组传送所需的发送缓冲器大小，并且即使周期开始分组的传输被延迟，其也可以给等时分组提供恒定的延迟。从输入侧总线接收的同步分组被输入到延迟部分，该同步分组根据延迟信息而被延迟并被发送到输出侧总线。输入侧和输出侧周期识别信息生成部分分别输出在周期开始分组被发送到输入侧总线和输出侧总线的定时变化的周期识别信息。输入侧基准周期识别信息生成部和输出侧基准周期识别信息生成部对预定定时的输入侧和输出侧周期识别信息进行采样，并输出输入侧和输出侧基准周期识别信息。延迟信息生成部基于输入侧和输出侧周期识别信息以及输入侧和输出侧基准周期识别信息，从预定定时向每个总线的经过循环次数的差添加固定延迟，生成延迟信息。

2. 发明授权

US06807194B1 Radio terminal station apparatus for SDH network and method of selecting operation clock thereof 有权
标题翻译： SDH网络无线终端装置及其操作时钟选择方法
公开(公告)号：US06807194B1
公开(公告)日：2004-10-19
申请号：US09248096
申请日：1999-02-11
申请人： Hideyuki Muto
发明人： Hideyuki Muto
IPC分类号： H04J306
CPC分类号： H04J3/0688 , H04J3/0691 , H04J2203/0035
摘要： A radio terminal station apparatus for an SDH network wherein the synchronous network construction never breaks, even when a wired transmission line is branched. In a multiplexing quality generation circuit for multiplexing and sending out quality information of a clock, the insertion direction and insertion system to multiplex the quality information are compared with the input direction and system providing the clock in the apparatus, and, in the case of the insertion system not being the system providing the clock in the apparatus and the insertion direction being opposite to the input direction of the clock in the apparatus and when the priority degree information of the system having an input direction opposite to the insertion direction is a special value defined in advance, the same quality information as the clock in the apparatus are multiplexed and sent out.
摘要翻译：一种用于SDH网络的无线电终端站装置，其中即使当有线传输线路分支时，同步网络构造也不会中断。在复用和发送时钟的质量信息的复用质量生成电路中，将质量信息复用的插入方向和插入系统与在设备中提供时钟的输入方向和系统进行比较，在插入系统不是在设备中提供时钟的系统，并且插入方向与设备中的时钟的输入方向相反，并且当具有与插入方向相反的输入方向的系统的优先级信息是特殊值时与设备中的时钟相同的质量信息被预先定义，并被发送出去。

3. 发明授权

US06785300B2 Delay compensation 失效
标题翻译：延迟补偿
公开(公告)号：US06785300B2
公开(公告)日：2004-08-31
申请号：US10272272
申请日：2002-10-17
申请人： Elliott Hoole
发明人： Elliott Hoole
IPC分类号： H04J306
CPC分类号： H04L5/026 , H04B1/69 , H04J3/0682 , H04L27/2646 , H04L27/2655 , H04L27/2675
摘要： In a discrete tone system, a base station receives a transmission burst from a remote unit being installed that includes delay compensation pilot tones that are uniformly spread throughout the transmission bandwidth. The arrival time transmission burst is not synchronized with the other remote units transmitting to the base station. The base station measures the phase delay of each tone and calculates the delay of the remote unit from the slope of the line of phase angle versus tone frequency. The base station transmits a signal to the remote unit that includes the magnitude and direction of the delay, which allows the remote unit to adapt the timing of its transmission to be synchronized with the other remote units.
摘要翻译：在离散音调系统中，基站从正在安装的远程单元接收传输突发，其包括在整个传输带宽上均匀分布的延迟补偿导频音调。到达时间传输脉冲串不与发送到基站的其他远程单元同步。基站测量每个音调的相位延迟，并根据相位角对音频的斜率计算远程单元的延迟。基站向远程单元发送包括延迟的大小和方向的信号，这允许远程单元使其传输的定时与其他远程单元同步。

4. 发明授权

US06771670B1 Time-alignment apparatus and method for time-aligning data frames of a plurality of channels in a telecommunication system 有权
标题翻译：一种用于在电信系统中对多个信道的数据帧进行时间对准的时间对准装置和方法
公开(公告)号：US06771670B1
公开(公告)日：2004-08-03
申请号：US09671616
申请日：2000-09-28
申请人： Jürgen Pfahler , Peter Jentsch
发明人： Jürgen Pfahler , Peter Jentsch
IPC分类号： H04J306
CPC分类号： H04B7/2678 , H04W56/005
摘要： In a telecommunication system where data frames of a plurality of channels (CH1,CH2. . . CHn) arrive with respective different time-offsets with respect to a common synchronization clock (WR, R/W, RD, T) of an internal frame structure of a decoder (DEC), three frame memories (RAM1, RAM2, RAM3) are used for performing a time-alignment of the data frames. The data frames are respectively written to two frame memories (RAM1, RAM2) having a read state and a reading of one frame memory (RAM3) is performed beginning with the occurrence of the common synchronization clock (T). A cyclic switching of the read/write state of the frame memories (RAM1, RAM2, RAM3) is performed, such that always two frame memories (RAM1, RAM2) are in a write-state (WR) and one frame memory (RAM3) is in a read-state (RD) The frame memory (RAM3) in the read-state is read out synchronized to the common synchronization clock.
摘要翻译：在多个信道（CH1，CH2 ... CHn）的数据帧相对于内部帧的公共同步时钟（WR，R / W，RD，T））到达不同时间偏移的电信系统中，使用解码器（DEC）的结构，三帧存储器（RAM1，RAM2，RAM3）用于执行数据帧的时间对准。数据帧分别被写入具有读取状态的两个帧存储器（RAM1，RAM2），并且从公共同步时钟（T）的出现开始执行一个帧存储器（RAM3）的读取。执行帧存储器（RAM1，RAM2，RAM3）的读/写状态的循环切换，使得总是两个帧存储器（RAM1，RAM2）处于写状态（WR）和一帧存储器（RAM3）处于读取状态（RD）读取状态的帧存储器（RAM3）被读出与公共同步时钟同步。

5. 发明授权

US06771669B1 Method and apparatus for remote memory clock synchronization for optimized leadoff performance 有权
标题翻译：用于远程存储器时钟同步的方法和装置，用于优化引导线性能
公开(公告)号：US06771669B1
公开(公告)日：2004-08-03
申请号：US09475458
申请日：1999-12-30
申请人： David J. McDonnell , Himanshu Sinha
发明人： David J. McDonnell , Himanshu Sinha
IPC分类号： H04J306
CPC分类号： H04L7/10 , H04L7/0037
摘要： A method and apparatus for synchronizing a synchronizing clock is disclosed for use in synchronizing a high-speed memory bus with a second, heritage memory bus. This method and apparatus includes generating an initial synchronizing clock from a reference clock of the high-speed memory bus. It then includes receiving a synchronizing packet on the high-speed memory bus utilizing the initial synchronizing clock. Finally, it includes delaying a clock transition of the initial synchronizing clock in response to the received data of the synchronizing packet.
摘要翻译：公开了用于使同步时钟同步的方法和装置，用于使高速存储器总线与第二遗留存储器总线同步。该方法和装置包括从高速存储器总线的参考时钟产生初始同步时钟。然后，它包括利用初始同步时钟在高速存储器总线上接收同步分组。最后，它包括响应于同步分组的接收数据延迟初始同步时钟的时钟转换。

6. 发明授权

US06757304B1 Method and apparatus for data communication and storage wherein a IEEE1394/firewire clock is synchronized to an ATM network clock 失效
标题翻译：用于数据通信和存储的方法和装置，其中IEEE1394 /火线时钟与ATM网络时钟同步
公开(公告)号：US06757304B1
公开(公告)日：2004-06-29
申请号：US09491280
申请日：2000-01-26
申请人： Takashi Nomura , Atsushi Maruyama
发明人： Takashi Nomura , Atsushi Maruyama
IPC分类号： H04J306
CPC分类号： H03L7/18 , H04L12/40058 , H04L12/40097 , H04L12/5601 , H04L2012/5665 , H04L2012/5674 , H04N5/765
摘要： The present invention relates to a data communication system for data communication between a bus and a network. This data communication system of the present invention includes a first interface device for performing interface processing for the bus, a second interface device for performing interface processing for the network, and a generating device for generating a first clock used by the first interface device in synchronization with a second clock used for causing processes in the network to be synchronized.
摘要翻译：本发明涉及一种用于总线与网络之间的数据通信的数据通信系统。本发明的数据通信系统包括用于对总线进行接口处理的第一接口装置，用于对网络进行接口处理的第二接口装置，以及用于同步地生成由第一接口装置使用的第一时钟的发生装置用于使网络中的进程同步的第二时钟。

7. 发明授权

US06757303B1 Technique for communicating time information 失效
标题翻译：沟通时间信息的技巧
公开(公告)号：US06757303B1
公开(公告)日：2004-06-29
申请号：US09272506
申请日：1999-03-19
申请人： Takeshi Kikuchi , Yuji Koike
发明人： Takeshi Kikuchi , Yuji Koike
IPC分类号： H04J306
CPC分类号： G10H1/0058 , G10H2210/391 , G10H2240/185 , G10H2240/295 , G10H2240/301 , G10H2240/305 , G10H2240/311 , G10H2240/315 , H04J3/0682 , H04L29/06027 , H04L65/602
摘要： A communication device comprises reception means for receiving externally supplied first time information representing time, time information generation means for generating second time information representing time, time difference detection means for detecting a time difference between the times represented by the received first time information and the second time information generated at a time point at which the first time information is received, and correction means for correcting the second time information generated by said time information generation means based on the received first time information when the time difference is greater than a predetermined value.
摘要翻译：一种通信装置，包括用于接收外部提供的表示时间的第一时间信息的接收装置，用于产生表示时间的第二时间信息的时间信息产生装置，用于检测由所接收的第一时间信息表示的时间与第二时间信息之间的时间差的时差检测装置在接收到第一时间信息的时间点产生的时间信息;以及校正装置，用于当时间差大于预定值时，基于接收到的第一时间信息来校正由所述时间信息产生装置产生的第二时间信息。

8. 发明授权

US06754235B2 Transmitter and receiver for a very high speed digital subscriber line 有权
标题翻译：用于高速数字用户线路的发射机和接收机
公开(公告)号：US06754235B2
公开(公告)日：2004-06-22
申请号：US09906531
申请日：2001-07-16
申请人： Frank Octaaf Van Der Putten , Paul Marie Pierre Spruyt
发明人： Frank Octaaf Van Der Putten , Paul Marie Pierre Spruyt
IPC分类号： H04J306
CPC分类号： H04J3/0638
摘要： To transparently transport an incoming clock signal (CLK2) with a known frequency over a network segment wherein transmission between a transmitter (TX) and a receiver (RX) operates synchronous to a transmit clock signal (CLK1) and receiver clock signal (CLK1′) which are synchronized, the transmitter measures the phase difference (P) between the incoming clock signal (CLK2) and a reference signal (R) obtained from the transmit clock signal (CLK1). The measured phase difference (P) is communicated to the receiver (RX) and used therein to generate a copy (CLK2)
摘要翻译：通过网络段以传输时钟信号（CLK2）透明传输已知频率，其中发射机（TX）和接收机（RX）之间的传输与传输时钟信号（CLK1）和接收机时钟信号（CLK1'）同步工作，发送器测量输入时钟信号（CLK2）和从发送时钟信号（CLK1）获得的参考信号（R）之间的相位差（P）。所测量的相位差（P）被传送到接收器（RX）并在其中使用以产生复制（CLK2）

9. 发明授权

US06754172B1 Non-interruptive protection switching device and network system using the same 失效
标题翻译：非中断保护开关器件和网络系统使用相同
公开(公告)号：US06754172B1
公开(公告)日：2004-06-22
申请号：US09723116
申请日：2000-11-27
申请人： Masayuki Tanaka , Masaki Kubo , Satoshi Nemoto , Shuji Sakakura , Shigeo Handa , Yuji Kamura
发明人： Masayuki Tanaka , Masaki Kubo , Satoshi Nemoto , Shuji Sakakura , Shigeo Handa , Yuji Kamura
IPC分类号： H04J306
CPC分类号： H04J3/0623 , H04J3/085 , H04J2203/0042 , H04J2203/006 , H04J2203/0096
摘要： A non-interruptive protection switching device which performs protection switching in a more efficient and robust way. The device has a working-channel signal storage unit to store data signals received through a working channel. Multiframe synchronization timings are detected by a working-channel multiframe synchronization controller, which provides a working-channel multiframe sync detection pulse signal when the main signals are in a normal condition and stops it when the channel is disrupted. A working-channel write controller controls every write access to the working-channel signal storage unit, generating a write pulse signal therefor. The working-channel write controller also produces working-channel write phase data by identifying a phase difference of the detected multiframe synchronization timing with respect to a reference phase signal. The generation of this write pulse signal is based on the multiframe sync detection pulse signal when the working-channel multiframe sync detection pulse signal is available, or on a free-running timebase when it is stopped. The stored data in the working- and protection-channel signal storage units are read out simultaneously, under the control of a read controller which produces read pulses from the write phase data.
摘要翻译：一种非中断保护切换装置，以更有效和鲁棒的方式进行保护倒换。该设备具有工作信道信号存储单元，用于存储通过工作信道接收的数据信号。多帧同步定时由工作信道复帧同步控制器检测，当主信号处于正常状态时，该帧同步控制器提供工作信道复帧同步检测脉冲信号，并在通道中断时停止。工作通道写入控制器控制对工作通道信号存储单元的每个写入访问，产生写入脉冲信号。工作通道写入控制器还通过相对于参考相位信号识别检测到的多帧同步定时的相位差来产生工作通道写入相位数据。当工作信道复帧同步检测脉冲信号可用时，或者在停止时的自由运行时基上，该写入脉冲信号的产生基于多帧同步检测脉冲信号。工作和保护通道信号存储单元中存储的数据在读写控制器的控制下被同时读出，读控制器从写相位数据产生读脉冲。

10. 发明授权

US06751235B1 Communication link synchronization method 有权
标题翻译：通信链路同步方法
公开(公告)号：US06751235B1
公开(公告)日：2004-06-15
申请号：US09604244
申请日：2000-06-27
申请人： Dean S. Susnow , Richard D. Reohr, Jr.
发明人： Dean S. Susnow , Richard D. Reohr, Jr.
IPC分类号： H04J306
CPC分类号： H04L7/10 , H04L2007/045
摘要： A communication link is synchronized by a network interface having a transmitter in a core clock domain different from the link clock domain of the communication link. A link synchronization state machine controls the link synchronization process. The functionality of the link synchronization state machine is partitioned so that some of the functions of the link synchronization process are performed by the transmitter in the core clock domain.
摘要翻译：通信链路由具有不同于通信链路的链路时钟域的核心时钟域中的发射机的网络接口同步。链路同步状态机控制链路同步过程。链路同步状态机的功能被分割，使得链路同步过程的一些功能由核心时钟域中的发射机执行。

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