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71. 发明申请

US20150060945A1 TRANSISTORS WITH HIGH CONCENTRATION OF BORON DOPED GERMANIUM 审中-公开
标题翻译：具有高浓度的硼氢化锗的晶体管
公开(公告)号：US20150060945A1
公开(公告)日：2015-03-05
申请号：US14535387
申请日：2014-11-07
申请人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
发明人： Anand S. Murthy , Glenn A. Glass , Tahir Ghani , Ravi Pillarisetty , Niloy Mukherjee , Jack T. Kavalieros , Roza Kotlyar , Willy Rachmady , Mark Y. Liu
IPC分类号： H01L29/36 , H01L21/02 , H01L29/78 , H01L29/66 , H01L29/165 , H01L29/08
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm−3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
摘要翻译：公开了用于形成具有高掺杂硼掺杂锗的源区和漏区的晶体管器件的技术。在一些实施例中，使用在源极和漏极区域及其对应的尖端区域中的选择性外延沉积来提供原位硼掺杂锗或者掺杂有硼掺杂锗层的硼掺杂硅锗。在一些这样的情况下，锗浓度可以例如超过50原子％且高达100原子％，并且硼浓度可以例如超过1E20cm-3。可以使用提供梯度锗和/或硼浓度的缓冲液来更好地接合不同的层。锗在外延金属界面掺杂的硼的浓度有效地降低了寄生电阻而不降低尖端突然性。这些技术可以例如在平面或非平面晶体管器件中实现。

72. 发明申请

US20130264639A1 COLUMN IV TRANSISTORS FOR PMOS INTEGRATION 有权
标题翻译：用于PMOS整合的柱IV晶体管
公开(公告)号：US20130264639A1
公开(公告)日：2013-10-10
申请号：US13990249
申请日：2011-12-20
申请人： Glenn A. Glass , Anand S. Murthy
发明人： Glenn A. Glass , Anand S. Murthy
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibit reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
摘要翻译：公开了用于形成具有高浓度锗的源/漏区的列IV晶体管器件的技术，并且相对于常规器件而言显示降低的寄生电阻。在一些示例性实施例中，源极/漏极区域各自包括薄的p型硅或锗或SiGe沉积，源/漏材料的其余部分沉积为p型锗或锗合金（例如，锗：锡或其他合适的应变诱导剂，并且锗含量为至少80原子％和20原子％以下的其他组分）。在某些情况下，可以在富锗盖层中观察到应变松弛的证据，包括失配位错和/或穿透位错和/或双胞胎。可以使用多个晶体管配置，包括平面和非平面晶体管结构（例如，FinFET和纳米线晶体管），以及应变和非限制的通道结构。

73. 发明申请

US20100207101A1 INCORPORATING GATE CONTROL OVER A RESONANT TUNNELING STRUCTURE IN CMOS TO REDUCE OFF-STATE CURRENT LEAKAGE, SUPPLY VOLTAGE AND POWER CONSUMPTION 有权
标题翻译：通过CMOS中的谐振隧道结构来控制栅极控制，以减少非状态电流泄漏，电源电压和功耗
公开(公告)号：US20100207101A1
公开(公告)日：2010-08-19
申请号：US12370844
申请日：2009-02-13
申请人： Leonard Franklin Register, II , Sanjay Banerjee
发明人： Leonard Franklin Register, II , Sanjay Banerjee
IPC分类号： H01L29/66 , H01L21/335
CPC分类号： H01L29/66977 , B82Y10/00 , H01L29/125 , H01L29/127 , H01L29/152 , H01L29/155 , H01L29/402 , H01L29/66931 , H01L29/66939
摘要： A semiconductor device and method for fabricating a semiconductor device incorporating gate control over a resonant tunneling structure. The semiconductor device includes a source terminal, a gate terminal, a drain terminal, and a resonant tunneling structure located beneath or adjacent to the gate terminal, where the gate terminal controls an electrostatic potential drop through the resonant tunneling structure as well as controlling a potential within a portion of the conduction channel immediately beneath the gate terminal as in a MOSFET. The semiconductor device is fabricated by growing epitaxial layers of tunnel barriers and quantum wells, where a quantum well is formed between each set of two tunneling barriers. Additionally, the epitaxial layers of tunnel barriers and quantum wells are grown, etched and patterned to form a resonant tunneling structure. Further, the semiconductor device is grown, etched and patterned to form a gate, source and drain electrode.
摘要翻译：一种用于制造在谐振隧道结构上并入栅极控制的半导体器件的半导体器件和方法。该半导体器件包括源极端子，栅极端子，漏极端子和位于栅极端子下方或相邻的谐振隧道结构，其中栅极端子控制通过谐振隧道结构的静电势下降以及控制电位在栅极端子正下方的导通通道的一部分内，如在MOSFET中。半导体器件通过生长隧道势垒和量子阱的外延层来制造，其中在每组两个隧道势垒之间形成量子阱。此外，隧道势垒和量子阱的外延层被生长，蚀刻和图案化以形成谐振隧道结构。此外，半导体器件被生长，蚀刻和图案化以形成栅极，源极和漏极。

74. 发明授权

US07569450B2 Semiconductor capacitors in hot (hybrid orientation technology) substrates 失效
标题翻译：热（混合取向技术）衬底中的半导体电容器
公开(公告)号：US07569450B2
公开(公告)日：2009-08-04
申请号：US11423284
申请日：2006-06-09
申请人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
发明人： Kangguo Cheng , Ramachandra Divakaruni , Carl John Radens
IPC分类号： H01L21/8242
CPC分类号： H01L29/945 , H01L29/66931
摘要： A semiconductor structure and a method for forming the same. The semiconductor structure includes a semiconductor substrate. The semiconductor structure further includes an electrically insulating region on top of the semiconductor substrate. The semiconductor structure further includes a first semiconductor region on top of and in direct physical contact with the semiconductor substrate. The semiconductor structure further includes a second semiconductor region on top of the insulating region. The semiconductor structure further includes a capacitor in the first semiconductor region and the semiconductor substrate. The semiconductor structure further includes a capacitor electrode contact in the second semiconductor region and the electrically insulating region.
摘要翻译：半导体结构及其形成方法。半导体结构包括半导体衬底。半导体结构还包括在半导体衬底的顶部上的电绝缘区域。半导体结构还包括在半导体衬底之上并与之直接物理接触的第一半导体区域。半导体结构还包括在绝缘区域的顶部上的第二半导体区域。半导体结构还包括在第一半导体区域和半导体衬底中的电容器。半导体结构还包括在第二半导体区域和电绝缘区域中的电容器电极接触。

75. 发明申请

US20080239625A1 ELECTRONIC COMPONENT MANUFACTURING METHOD 有权
标题翻译：电子元件制造方法
公开(公告)号：US20080239625A1
公开(公告)日：2008-10-02
申请号：US12059497
申请日：2008-03-31
申请人： Oliver Kermarrec , Daniel Bensahel , Yves Campidelli
发明人： Oliver Kermarrec , Daniel Bensahel , Yves Campidelli
IPC分类号： H01G4/228 , H01L21/20 , H01L33/00
CPC分类号： H01L29/66931 , H01L29/66136 , H01L29/861 , H01L29/945
摘要： A method for manufacturing an electronic component on a semiconductor substrate, including forming at least one opening in the substrate; forming in the bottom and on the walls of the opening and on the substrate an alternated succession of layers of a first material and of a second material, the second material being selectively etchable with respect to the first material and the substrate; trimming the layer portions of the first material and of the second material which are not located in the opening; selectively etching a portion of the first material to obtain trenches; and filling the trenches with at least one third material.
摘要翻译：一种在半导体衬底上制造电子部件的方法，包括在所述衬底中形成至少一个开口; 在所述开口的底部和所述壁的所述基板上形成交替连续的第一材料层和第二材料层，所述第二材料相对于所述第一材料和所述基板可选择性地蚀刻; 修剪不位于开口中的第一材料和第二材料的层部分; 选择性蚀刻第一材料的一部分以获得沟槽; 并用至少一个第三材料填充沟槽。

76. 发明授权

US5562802A Method of producing a quantum device which utilizes the quantum effect 失效
标题翻译：使用量子效应的量子器件的制造方法
公开(公告)号：US5562802A
公开(公告)日：1996-10-08
申请号：US419179
申请日：1995-04-10
申请人： Kenji Okada , Kiyoshi Morimoto , Masaharu Udagawa , Koichiro Yuki , Masaaki Niwa , Yoshihiko Hirai , Juro Yasui
发明人： Kenji Okada , Kiyoshi Morimoto , Masaharu Udagawa , Koichiro Yuki , Masaaki Niwa , Yoshihiko Hirai , Juro Yasui
IPC分类号： H01L29/06 , H01L21/334 , H01L29/10 , H01L29/68 , H01L29/772 , H01L29/88 , B44C1/22 , C03C15/00 , H01L29/161
CPC分类号： B82Y10/00 , B82Y30/00 , H01L29/1037 , H01L29/66931 , H01L29/772 , H01L29/882 , Y10S438/911 , Y10S438/962
摘要： A quantum device including a plate-like conductor part having a necking portion and a method of producing the same are disclosed. The method includes the steps of forming a first mask layer having a first strip portion on a conductor substrate; forming a second mask layer having a second strip portion on the conductor substrate; etching a region of the conductor substrate which is not covered with the first and second mask layers, by using the first and second mask layers as an etching mask, to form a plurality of first recess portions on a surface of the conductor substrate; selectively covering side faces of the plurality of first recess portions, and side faces of the first and second mask layers with a side wall film; selectively removing only the second mask layer, the first mask layer and the side wall film being left unremoved; etching another region of the conductor substrate which is not covered with the first mask layer and the side wall film, by using the first mask layer and the side wall film as an etching mask, to form a plurality of second recess portions on the surface of the conductor substrate; selectively removing part of another region of the surface of the conductor substrate which is not covered with the first mask layer and the side wall film; and removing the first mask layer and the side wall film, to form the plate-like conductor part having the necking portion at the conductor substrate.
摘要翻译：公开了一种包括具有颈缩部的板状导体部的量子装置及其制造方法。该方法包括以下步骤：在导体基板上形成具有第一条带部分的第一掩模层; 在所述导体基板上形成具有第二带状部分的第二掩模层; 通过使用第一和第二掩模层作为蚀刻掩模蚀刻未被第一和第二掩模层覆盖的导体基板的区域，以在导体基板的表面上形成多个第一凹部; 选择性地覆盖所述多个第一凹部的侧面，所述第一和第二掩模层的侧面具有侧壁膜; 仅选择性地除去第二掩模层，第一掩模层和侧壁膜不被去除; 通过使用第一掩模层和侧壁膜作为蚀刻掩模蚀刻未被第一掩模层和侧壁膜覆盖的导体基板的另一区域，以在第一掩模层和侧壁膜的表面上形成多个第二凹部导体基板; 选择性地去除未被第一掩模层和侧壁膜覆盖的导体基板的表面的另一区域的一部分; 并且去除第一掩模层和侧壁膜，以在导体基板上形成具有颈缩部分的板状导体部分。

77. 发明授权

US5371038A Method of forming a quantum multi-function semiconductor device 失效
标题翻译：形成量子多功能半导体器件的方法
公开(公告)号：US5371038A
公开(公告)日：1994-12-06
申请号：US139180
申请日：1993-10-21
申请人： Raymond K. Tsui
发明人： Raymond K. Tsui
IPC分类号： H01L29/06 , H01L21/20 , H01L21/334 , H01L29/66 , H01L29/76
CPC分类号： H01L29/66931 , H01L21/02392 , H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02546 , H01L21/02549 , H01L21/02639 , H01L21/02647 , H01L29/7606 , Y10S438/908
摘要： The present invention is a method of forming a quantum multi-function semiconductor device. In the method of the present invention, an insulating layer (12) is formed on a semiconductor substrate (11). An opening (14) is formed in the insulating layer (12), and a channel region (15) is formed in the opening (14). A channel layer (21) is formed over the channel region (15). An opening (23) is formed through the channel layer (21) such that a portion of the opening is over a portion of the channel region (15). A source electrode (28) is formed to contact a channel layer (17) of the channel region (15), a drain electrode (29) is formed to contact the channel layer (21), and a gate electrode (31) is formed to contact the second barrier layer (27).
摘要翻译：本发明是形成量子多功能半导体器件的方法。在本发明的方法中，在半导体衬底（11）上形成绝缘层（12）。在所述绝缘层（12）中形成开口（14），并且在所述开口（14）中形成沟道区域（15）。沟道层（21）形成在沟道区域（15）上。通过通道层（21）形成开口（23），使得开口的一部分在通道区域（15）的一部分之上。源电极（28）形成为与沟道区（15）的沟道层（17）接触，形成漏电极（29）与沟道层（21）接触，形成栅电极以接触第二阻挡层（27）。

78. 发明授权

US5318916A Symmetric self-aligned processing 失效
标题翻译：对称自对准处理
公开(公告)号：US5318916A
公开(公告)日：1994-06-07
申请号：US923254
申请日：1992-07-31
申请人： Paul M. Enquist , David B. Slater, Jr.
发明人： Paul M. Enquist , David B. Slater, Jr.
IPC分类号： H01L21/306 , H01L21/331 , H01L21/334 , H01L21/265
CPC分类号： H01L29/66931 , H01L21/30621 , H01L29/66318 , Y10S148/012 , Y10S148/135 , Y10S438/928 , Y10S438/97
摘要： A method of manufacturing a semiconductor device using simplified processing and eliminating and/or minimizing the extrinsic parasitic elements of the device. The method is particularly suited for manufacturing heterojunction bipolar transistors where the extrinsic parasitic base resistance and the extrinsic parasitic base-collector and base-emitter capacitances can be virtually eliminated and the base contact resistance can be greatly reduced. The method includes formming symmetric emitter and collector portions using front and backside processing of the wafer, respectively. The symmetric emitter and collector virtually eliminates the extrinsic collector and emitter regions of the device thereby virtually eliminating the extrinsic base-collector and base-emitter capacitance. The extrinsic base contact region may also be increased to minimize the base contact resistance without increasing parasitic capacitive elements of the device. Self-aligned processing features are also included to form self-aligned contacts to the base layer thereby virtually eliminating the extrinsic base resistance. The method may include building up the collector and emitter contacts to separate the emitter and collector interconnections from the base layer to avoid increasing the emitter-base and collector-base extrinsic parasitic capacitances and to minimize associated resistances and inductances. The method may further include forming etch stop layers to facilitate removing of the substrate to perform the backside processing and to accurately etch through the collector layer without etching the base layer.
摘要翻译：使用简化处理制造半导体器件的方法，并且消除和/或最小化器件的外在寄生元件。该方法特别适用于制造异质结双极晶体管，其中可以实际上消除外部寄生基极电阻和外部寄生基极集电极和基极 - 发射极电容，并且可大大降低基极接触电阻。该方法包括分别使用晶片的正面和背面处理来形成对称的发射极和集电极部分。对称发射极和集电极实际上消除了器件的非本征集电极和发射极区域，从而实际上消除了外部基极集电极和基极 - 发射极电容。也可以增加非本征基极接触区域以使基极接触电阻最小化，而不增加器件的寄生电容元件。还包括自对准处理特征以形成与基层的自对准接触，从而实际上消除了外部基极电阻。该方法可以包括建立集电极和发射极触点以将发射极和集电极互连与基极层分离，以避免增加发射极 - 基极和集电极 - 基极外部寄生电容并且使相关联的电阻和电感最小化。该方法还可以包括形成蚀刻停止层以便于去除衬底以执行背面处理，并且在不蚀刻基底层的情况下精确地蚀刻通过集电极层。

79. 发明专利

JP2014508396A Transistor devices, integrated circuit and a method for manufacturing 有权
公开(公告)号：JP2014508396A
公开(公告)日：2014-04-03
申请号：JP2013546324
申请日：2011-12-20
申请人：インテルコーポレイション
发明人：エー．グラス，グレン , エス．マーシー，アナンド
IPC分类号： H01L21/336 , B82Y30/00 , B82Y40/00 , H01L21/28 , H01L29/06 , H01L29/41 , H01L29/78 , H01L29/786
CPC分类号： H01L29/0676 , H01L21/02532 , H01L21/28512 , H01L21/28525 , H01L21/3215 , H01L21/76831 , H01L23/535 , H01L27/092 , H01L27/0924 , H01L29/0615 , H01L29/0847 , H01L29/086 , H01L29/165 , H01L29/167 , H01L29/36 , H01L29/41791 , H01L29/42392 , H01L29/45 , H01L29/456 , H01L29/4966 , H01L29/66477 , H01L29/66545 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/66681 , H01L29/66931 , H01L29/7785 , H01L29/78 , H01L29/7816 , H01L29/7833 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要：高濃度のゲルマニウムのソース/ドレイン領域を有し、従来の装置と比較して低い規制抵抗を示す第IV列トランジスタ装置を形成する技術が開示される。一実施形態では、ソース/ドレイン領域の各々は薄いp型シリコン又はゲルマニウム又はSiGeの堆積部を含み、ソース/ドレイン材料堆積部の残りはp型ゲルマニウム又はゲルマニウム合金(例えば、ゲルマニウム：スズ又は他の適切な歪み誘起部であり、少なくとも80原子％のゲルマニウム成分と20原子％未満の他の成分とを有する)である。この場合、歪み緩和効果がゲルマニウムリッチキャップ層で確認され、ミスフィット転移及び/又は貫通転移及び/又はツインズを含む。プレーナ及び非プレーナトランジスタ構造(例えば、FinFET及びナノワイヤトランジスタ)の双方だけでなく、歪みのある又は歪みのないチャネル構造も含む様々なトランジスタ構造を使用することができる。

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