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1. 发明授权

US5684308A CMOS-compatible InP/InGaAs digital photoreceiver 失效
标题翻译： CMOS兼容InP / InGaAs数字光电接收器
公开(公告)号：US5684308A
公开(公告)日：1997-11-04
申请号：US601904
申请日：1996-02-15
申请人： Michael L. Lovejoy , Benny H. Rose , David C. Craft , Paul M. Enquist , David B. Slater, Jr.
发明人： Michael L. Lovejoy , Benny H. Rose , David C. Craft , Paul M. Enquist , David B. Slater, Jr.
IPC分类号： H01L27/144 , H01L31/0232
CPC分类号： H01L27/1443
摘要： A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.
摘要翻译：数字光接收器在InP半导体衬底上单片形成，并且包括由通过外延生长工艺沉积的多个InP / InGaAs层和由相同InP / InGaAs层形成的相邻异质结双极晶体管（HBT）放大器形成的p-i-n光电检测器。光接收放大器工作在大信号模式，以将检测到的光电流信号转换成能够直接驱动诸如CMOS的集成电路的放大输出。结合光发射机，光接收器可用于建立集成电路与多芯片模块（MCM）应用之间的数字光通信的短距离通道。光接收器还可以与光纤耦合一起使用，用于在分布式计算机之间建立较长范围的数字通信（即光学互连）等。数字光接收器的阵列可以形成在公共衬底上，用于建立多个数字光通信通道，每个光接收器间隔小于约1mm，消耗小于约20mW的功率，优选小于约10mW 。这样的光接收器阵列可用于以高达约1000Mb / s或更高的比特率在集成电路之间传送大量的数字数据。

2. 发明授权

US5318916A Symmetric self-aligned processing 失效
标题翻译：对称自对准处理
公开(公告)号：US5318916A
公开(公告)日：1994-06-07
申请号：US923254
申请日：1992-07-31
申请人： Paul M. Enquist , David B. Slater, Jr.
发明人： Paul M. Enquist , David B. Slater, Jr.
IPC分类号： H01L21/306 , H01L21/331 , H01L21/334 , H01L21/265
CPC分类号： H01L29/66931 , H01L21/30621 , H01L29/66318 , Y10S148/012 , Y10S148/135 , Y10S438/928 , Y10S438/97
摘要： A method of manufacturing a semiconductor device using simplified processing and eliminating and/or minimizing the extrinsic parasitic elements of the device. The method is particularly suited for manufacturing heterojunction bipolar transistors where the extrinsic parasitic base resistance and the extrinsic parasitic base-collector and base-emitter capacitances can be virtually eliminated and the base contact resistance can be greatly reduced. The method includes formming symmetric emitter and collector portions using front and backside processing of the wafer, respectively. The symmetric emitter and collector virtually eliminates the extrinsic collector and emitter regions of the device thereby virtually eliminating the extrinsic base-collector and base-emitter capacitance. The extrinsic base contact region may also be increased to minimize the base contact resistance without increasing parasitic capacitive elements of the device. Self-aligned processing features are also included to form self-aligned contacts to the base layer thereby virtually eliminating the extrinsic base resistance. The method may include building up the collector and emitter contacts to separate the emitter and collector interconnections from the base layer to avoid increasing the emitter-base and collector-base extrinsic parasitic capacitances and to minimize associated resistances and inductances. The method may further include forming etch stop layers to facilitate removing of the substrate to perform the backside processing and to accurately etch through the collector layer without etching the base layer.
摘要翻译：使用简化处理制造半导体器件的方法，并且消除和/或最小化器件的外在寄生元件。该方法特别适用于制造异质结双极晶体管，其中可以实际上消除外部寄生基极电阻和外部寄生基极集电极和基极 - 发射极电容，并且可大大降低基极接触电阻。该方法包括分别使用晶片的正面和背面处理来形成对称的发射极和集电极部分。对称发射极和集电极实际上消除了器件的非本征集电极和发射极区域，从而实际上消除了外部基极集电极和基极 - 发射极电容。也可以增加非本征基极接触区域以使基极接触电阻最小化，而不增加器件的寄生电容元件。还包括自对准处理特征以形成与基层的自对准接触，从而实际上消除了外部基极电阻。该方法可以包括建立集电极和发射极触点以将发射极和集电极互连与基极层分离，以避免增加发射极 - 基极和集电极 - 基极外部寄生电容并且使相关联的电阻和电感最小化。该方法还可以包括形成蚀刻停止层以便于去除衬底以执行背面处理，并且在不蚀刻基底层的情况下精确地蚀刻通过集电极层。

3. 发明授权

US5272095A Method of manufacturing heterojunction transistors with self-aligned metal contacts 失效
标题翻译：具有自对准金属触点的异质结晶体管的制造方法
公开(公告)号：US5272095A
公开(公告)日：1993-12-21
申请号：US853439
申请日：1992-03-18
申请人： Paul M. Enquist , David B. Slater, Jr.
发明人： Paul M. Enquist , David B. Slater, Jr.
IPC分类号： H01L21/331 , H01L21/334 , H01L21/60 , H01L29/08 , H01L29/737 , H01L21/265 , H01L29/70
CPC分类号： H01L21/76897 , H01L29/0817 , H01L29/66318 , H01L29/66931 , H01L29/7371 , Y10S148/072
摘要： A method of manufacturing heterojunction transistors having self-aligned contacts. In manufacturing a heterojunction bipolar transistor, a collector and a base layer are deposited on a substrate. A masking layer is deposited on the base layer and selectively etched to form an aperture therein, exposing the base layer. An emitter having a mesa structure is grown epitaxially on the exposed base layer to produce lateral overhang portions. The overhang portions may be formed by continuing the epitaxial growth to form lateral overgrowth portions overlapping the masking material. The masking layer is removed and self-aligned contacts are formed to the base and emitter regions using the lateral overhang portions which provide separation between the emitter structure and the contacts to the base layer.
摘要翻译：一种具有自对准触点的异质结晶体管的制造方法。在制造异质结双极晶体管时，将集电极和基极层沉积在衬底上。掩模层沉积在基层上并选择性地蚀刻以在其中形成孔，暴露基层。具有台面结构的发射体在暴露的基底层上外延生长以产生横向伸出部分。可以通过继续外延生长形成与掩模材料重叠的横向过度生长部分来形成突出部分。去除掩模层，并使用提供发射极结构和与基底层的触点之间的间隔的横向突出部分，将基底和发射极区域形成自对准触点。

4. 发明授权

US08735219B2 Heterogeneous annealing method and device 有权
标题翻译：异相退火方法及装置
公开(公告)号：US08735219B2
公开(公告)日：2014-05-27
申请号：US13599023
申请日：2012-08-30
申请人： Paul M. Enquist , Gaius Gillman Fountain
发明人： Paul M. Enquist , Gaius Gillman Fountain
IPC分类号： H01L21/48
CPC分类号： H01L25/0657 , H01L21/2007 , H01L21/6835 , H01L21/76898 , H01L23/49866 , H01L24/32 , H01L24/83 , H01L25/50 , H01L2221/68359 , H01L2224/29147 , H01L2224/29155 , H01L2224/83053 , H01L2224/83201 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
摘要翻译：一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。第一绝缘材料直接接合到第二绝缘材料上。去除第一衬底的一部分以留下剩余部分。具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。粘合的基底被加热以促进第一和第二接触结构之间的电接触。在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

5. 发明授权

US08426248B2 Room temperature metal direct bonding 有权
公开(公告)号：US08426248B2
公开(公告)日：2013-04-23
申请号：US12913385
申请日：2010-10-27
申请人： Qin-Yi Tong , Paul M. Enquist , Anthony Scot Rose
发明人： Qin-Yi Tong , Paul M. Enquist , Anthony Scot Rose
IPC分类号： H01L21/00
摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.

6. 发明授权

US08389378B2 3D IC method and device 有权
公开(公告)号：US08389378B2
公开(公告)日：2013-03-05
申请号：US12270585
申请日：2008-11-13
申请人： Paul M. Enquist , Gaius Gillman Fountain, Jr. , Qin-Yi Tong
发明人： Paul M. Enquist , Gaius Gillman Fountain, Jr. , Qin-Yi Tong
IPC分类号： H01L31/102
CPC分类号： H01L21/76838 , H01L21/76898 , H01L23/481 , H01L24/02 , H01L24/81 , H01L24/94 , H01L24/97 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2224/0401 , H01L2224/81121 , H01L2224/81201 , H01L2224/8123 , H01L2224/81801 , H01L2224/81894 , H01L2224/81931 , H01L2224/83894 , H01L2224/9202 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01046 , H01L2924/01049 , H01L2924/0105 , H01L2924/01055 , H01L2924/01059 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/19043 , H01L2924/3025 , H01L2224/81
摘要： A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

7. 发明授权

US06984571B1 Three dimensional device integration method and integrated device 有权
公开(公告)号：US06984571B1
公开(公告)日：2006-01-10
申请号：US09410054
申请日：1999-10-01
申请人： Paul M. Enquist
发明人： Paul M. Enquist
IPC分类号： H01L29/06
CPC分类号： H01L24/08 , H01L21/187 , H01L21/2007 , H01L21/6835 , H01L21/76251 , H01L21/76898 , H01L21/8221 , H01L23/13 , H01L23/36 , H01L23/481 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L23/552 , H01L24/24 , H01L24/26 , H01L24/27 , H01L24/30 , H01L24/48 , H01L24/80 , H01L24/82 , H01L24/83 , H01L24/94 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/16 , H01L25/167 , H01L25/18 , H01L25/50 , H01L27/0688 , H01L27/14634 , H01L2221/6835 , H01L2221/68359 , H01L2221/68363 , H01L2223/6677 , H01L2224/0807 , H01L2224/08123 , H01L2224/1134 , H01L2224/16 , H01L2224/24011 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/3005 , H01L2224/30104 , H01L2224/305 , H01L2224/48091 , H01L2224/48101 , H01L2224/48227 , H01L2224/48247 , H01L2224/80896 , H01L2224/81894 , H01L2224/8303 , H01L2224/83092 , H01L2224/83099 , H01L2224/8319 , H01L2224/83193 , H01L2224/83345 , H01L2224/83359 , H01L2224/8385 , H01L2224/83894 , H01L2224/83896 , H01L2224/83912 , H01L2224/83948 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06555 , H01L2225/06589 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01074 , H01L2924/01082 , H01L2924/0132 , H01L2924/014 , H01L2924/05442 , H01L2924/07802 , H01L2924/10253 , H01L2924/10329 , H01L2924/1305 , H01L2924/13062 , H01L2924/13063 , H01L2924/13064 , H01L2924/13091 , H01L2924/14 , H01L2924/1461 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/351 , Y10S148/012 , Y10S438/977 , H01L2224/13099 , H01L2924/01049 , H01L2924/01031 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/8203 , H01L2224/821 , H01L2224/80001 , H01L2224/82
摘要： A device integration method and integrated device. The method includes the steps of polishing surfaces of first and second workpieces each to a surface roughness of about 5–10 Å. The polished surfaces of the first and second workpieces are bonded together. A surface of a third workpiece is polished to the surface roughness. The surface of the third workpiece is bonded to the joined first and second workpieces. The first, second and third workpieces may each be a semiconductor device having a thin material formed on one surface, preferably in wafer form. The thin materials are polished to the desired surface roughness and then bonded together. The thin materials may each have a thickness of approximately 1–10 times the surface non-planarity of the material on which they are formed. Any number of devices may be bonded together, and the devices may be different types of devices or different technologies.

8. 发明申请

US20140061949A1 HETEROGENEOUS ANNEALING METHOD AND DEVICE 有权
标题翻译：异构退火方法和装置
公开(公告)号：US20140061949A1
公开(公告)日：2014-03-06
申请号：US13599023
申请日：2012-08-30
申请人： Paul M. Enquist , Gaius Gillman Fountain, JR.
发明人： Paul M. Enquist , Gaius Gillman Fountain, JR.
IPC分类号： H01L21/603 , H01L25/00
CPC分类号： H01L25/0657 , H01L21/2007 , H01L21/6835 , H01L21/76898 , H01L23/49866 , H01L24/32 , H01L24/83 , H01L25/50 , H01L2221/68359 , H01L2224/29147 , H01L2224/29155 , H01L2224/83053 , H01L2224/83201 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having a second surface with a second insulating material and a second contact structure. The first insulating material is directly bonded to the second insulating material. A portion of the first substrate is removed to leave a remaining portion. A third substrate having a coefficient of thermal expansion (CTE) substantially the same as a CTE of the first substrate is bonded to the remaining portion. The bonded substrates are heated to facilitate electrical contact between the first and second contact structures. The third substrate is removed after heating to provided a bonded structure with reliable electrical contacts.
摘要翻译：一种将具有第一表面的第一衬底与第一绝缘材料和第一接触结构与具有第二表面的第二衬底与第二绝缘材料和第二接触结构集成的方法。第一绝缘材料直接接合到第二绝缘材料上。去除第一衬底的一部分以留下剩余部分。具有与第一基板的CTE基本相同的热膨胀系数（CTE）的第三基板被结合到剩余部分。粘合的基底被加热以促进第一和第二接触结构之间的电接触。在加热之后移除第三衬底以提供具有可靠电接触的接合结构。

9. 发明申请

US20110041329A1 ROOM TEMPERATURE METAL DIRECT BONDING 有权
标题翻译：房间温度金属直接结合
公开(公告)号：US20110041329A1
公开(公告)日：2011-02-24
申请号：US12913385
申请日：2010-10-27
申请人： Qin-Yi Tong , Paul M. Enquist , Anthony Scot Rose
发明人： Qin-Yi Tong , Paul M. Enquist , Anthony Scot Rose
IPC分类号： H05K3/36
CPC分类号： H01L21/76251 , B23K20/02 , H01L21/481 , H01L24/09 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/28 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/89 , H01L24/90 , H01L25/50 , H01L2224/05568 , H01L2224/05573 , H01L2224/13011 , H01L2224/13099 , H01L2224/13109 , H01L2224/13144 , H01L2224/13147 , H01L2224/32145 , H01L2224/80801 , H01L2224/81011 , H01L2224/81013 , H01L2224/81014 , H01L2224/81136 , H01L2224/81143 , H01L2224/81193 , H01L2224/81208 , H01L2224/8121 , H01L2224/81801 , H01L2224/81815 , H01L2224/8183 , H01L2224/81894 , H01L2224/83095 , H01L2224/8319 , H01L2224/8334 , H01L2224/83801 , H01L2224/8383 , H01L2224/8384 , H01L2224/8385 , H01L2224/83894 , H01L2224/83895 , H01L2224/83907 , H01L2224/9202 , H01L2225/06513 , H01L2924/00013 , H01L2924/01003 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/0106 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/07802 , H01L2924/10329 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1532 , H01L2924/351 , Y10T29/49126 , H01L2924/3512 , H01L2924/00 , H01L2224/29099 , H01L2224/05644 , H01L2924/00014 , H01L2224/05664 , H01L2224/05669 , H01L2224/05124 , H01L2224/05147
摘要： A bonded device structure including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads formed by contact bonding of the first non-metallic region to the second non-metallic region. At least one of the first and second substrates may be elastically deformed.
摘要翻译：一种粘结器件结构，包括具有第一组金属接合焊盘的第一衬底，优选地连接到器件或电路，并且具有与第一衬底上的金属焊盘相邻的第一非金属区域，第二衬底具有第二衬底一组金属接合焊盘与第一组金属焊盘对准，优选地连接到器件或电路，并且具有与第二衬底上的金属焊盘相邻的第二非金属区域，以及位于第二衬底之间的接触接合界面通过第一非金属区域与第二非金属区域的接触接合形成的第一和第二组金属接合焊盘。第一和第二基板中的至少一个可能弹性变形。

10. 发明授权

US07622324B2 Wafer bonding hermetic encapsulation 有权
标题翻译：晶圆粘合气密封装
公开(公告)号：US07622324B2
公开(公告)日：2009-11-24
申请号：US10913357
申请日：2004-08-09
申请人： Paul M. Enquist , Qin-Yi Tong , Gaius Gillman Fountain, Jr. , Robert Markunas
发明人： Paul M. Enquist , Qin-Yi Tong , Gaius Gillman Fountain, Jr. , Robert Markunas
IPC分类号： H01L21/00
CPC分类号： B81C1/00269 , B81C2203/0118 , H01L21/50 , H01L23/10 , H01L2924/0002 , H01L2924/01079 , H01L2924/00
摘要： A method for providing encapsulation of an electronic device which obtains an encapsulating member configured to enclose the electronic device, prepares a surface of the encapsulating member for non-adhesive direct bonding, prepares a surface of a device carrier including the electronic device for non-adhesive direct bonding, and bonds the prepared surface of the encapsulating member to the prepared surface of the device carrier to form an encapsulation of the electronic device. As such, an encapsulated electronic device results which includes the device carrier having a first bonding region encompassing the electronic device, includes the encapsulating member having at least one relief preventing contact between the electronic device and the encapsulating member and having a second bonding region bonded to the first bonding region of the device carrier, and includes a non-adhesive direct bond formed between the first and second bonding regions thereby to form an encapsulation of the electronic device. The encapsulated electronic device can be an electronic or optoelectronic device.
摘要翻译：一种用于提供电子设备的封装的方法，该电子设备获得构造成封闭电子设备的封装构件，准备用于非粘合剂直接接合的封装构件的表面，准备包括用于非粘合剂的电子设备的设备载体的表面直接结合，并将封装构件的制备表面粘合到装置载体的制备表面上以形成电子器件的封装。因此，包括具有包围电子设备的第一接合区域的器件载体的封装的电子器件包括具有至少一个防止接触电子器件与封装元件之间的防止接触的封装元件，并且具有第二接合区域装置载体的第一结合区域，并且包括在第一和第二接合区域之间形成的非粘合性直接结合，从而形成电子器件的封装。封装的电子器件可以是电子或光电器件。

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