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71. 发明授权

US07023044B2 Stacked capacitor-type semiconductor storage device and manufacturing method thereof 失效
公开(公告)号：US07023044B2
公开(公告)日：2006-04-04
申请号：US10893914
申请日：2004-07-20
申请人： Yusuke Kohyama , Takashi Ohsawa , Shizuo Sawada
发明人： Yusuke Kohyama , Takashi Ohsawa , Shizuo Sawada
IPC分类号： H01L27/108 , H01L29/76
CPC分类号： H01L27/10888 , H01L21/76831 , H01L21/76834 , H01L21/76897 , H01L27/0207 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.

72. 发明申请

US20060046408A1 Semiconductor integrated device 失效
标题翻译：半导体集成器件
公开(公告)号：US20060046408A1
公开(公告)日：2006-03-02
申请号：US11092920
申请日：2005-03-30
申请人： Takashi Ohsawa
发明人： Takashi Ohsawa
IPC分类号： H01L21/331
CPC分类号： H01L29/7322 , H01L27/1203 , H01L29/735 , H01L29/8611
摘要： A semiconductor integrated apparatus, comprising: an SOI (Silicon On Insulator) substrate which has a support substrate and an embedded insulation film; an NMOSFET, a PMOSFET and an FBC (Floating Body Cell) formed on the SOI substrate separately from each other; a p type of first well diffusion region formed along the embedded insulation film in the support substrate below the NMOSFET; an n type of second well diffusion region formed along the embedded insulation film in the support substrate below the PMOSFET; and a conduction type of third well diffusion region formed along the embedded insulation film in the support substrate below the FBC.
摘要翻译：一种半导体集成装置，包括：具有支撑衬底和嵌入绝缘膜的SOI（绝缘体上硅）衬底; 在SOI衬底上彼此分开形成的NMOSFET，PMOSFET和FBC（浮动体电池）; 沿着NMOSFET下方的支撑衬底中的嵌入绝缘膜形成的p型第一阱扩散区; 沿着PMOSFET下方的支撑衬底中的嵌入式绝缘膜形成的n型第二阱扩散区; 以及沿着FBC下方的支撑衬底中的嵌入绝缘膜形成的导电类型的第三阱扩散区域。

73. 发明申请

US20060044794A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060044794A1
公开(公告)日：2006-03-02
申请号：US11056243
申请日：2005-02-14
申请人： Kosuke Hatsuda , Takashi Ohsawa , Katsuyuki Fujita
发明人： Kosuke Hatsuda , Takashi Ohsawa , Katsuyuki Fujita
IPC分类号： F21S2/00
CPC分类号： G11C7/14 , G11C11/404 , G11C11/4091 , G11C11/4099 , G11C2211/4016
摘要： A semiconductor memory device comprises memory cells that store data by accumulating or discharging an electric charge; memory cell arrays that have a plurality of the memory cells disposed in a matrix; a plurality of word lines that are connected to the memory cells arrayed in rows of the memory cell arrays; a plurality of bit lines that are connected to the memory cells arrayed in columns of the memory cell arrays; a plurality of dummy cells that are arrayed in a row direction of the memory cell arrays and are connected to the bit lines; sense amplifiers that detect data within the memory cells by using an average value of electric characteristics of the dummy cells that plurality of switching elements that electrically connect four or more of the bit lines in order to generate the reference signal.
摘要翻译：半导体存储器件包括通过累积或放电来存储数据的存储器单元; 具有设置在矩阵中的多个存储单元的存储单元阵列; 连接到排列在存储单元阵列中的存储单元的多个字线; 连接到排列在存储单元阵列的列中的存储单元的多个位线; 多个虚拟单元，其被布置在存储单元阵列的行方向上并连接到位线; 读出放大器，通过使用电连接四个或更多个位线的多个开关元件的虚拟单元的电特性的平均值来检测存储单元内的数据，以便产生参考信号。

74. 发明授权

US06980474B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06980474B2
公开(公告)日：2005-12-27
申请号：US10882354
申请日：2004-07-02
申请人： Takashi Ohsawa
发明人： Takashi Ohsawa
IPC分类号： H01L27/108 , G11C5/00 , G11C7/00 , G11C7/02 , G11C11/14 , G11C11/401 , G11C11/404 , H01L21/8242 , H01L29/786
CPC分类号： G11C11/14 , H01L29/7841
摘要： A semiconductor memory device disclosed herein has a memory cell array in which memory cells are arranged in a matrix form, data being written into each of the memory cells by passing a cell current therethrough; word lines which are provided in parallel along a row direction in the memory cell array; bit lines which are provided in parallel along a column direction in the memory cell array, the column direction being crossed with the row direction; sense amplifiers which are respectively connected to the bit lines and which write data held in the sense amplifiers into the memory cells; a data line which supplies data to be written into the sense amplifiers; and a control circuit which, in a continuous write operation of performing write operations by continuously switching a column address to select a column, opens only a connection between the sense amplifier selected by the column address and the bit line to write the data held in the sense amplifier into the memory cell.
摘要翻译：本文公开的半导体存储器件具有存储单元阵列，其中以矩阵形式布置存储器单元，通过使单元电流通过其中而将数据写入每个存储单元; 在存储单元阵列中沿着行方向并行设置的字线; 在存储单元阵列中沿列方向并行设置的位线，列方向与行方向交叉; 感测放大器，其分别连接到位线，并且将保持在读出放大器中的数据写入存储单元; 提供要写入读出放大器的数据的数据线; 以及控制电路，在通过连续地切换列地址以选择列来进行写入操作的连续写入操作中，仅打开由列地址选择的读出放大器与位线之间的连接，以将保持在读出放大器进入存储单元。

75. 发明申请

US20050093064A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
标题翻译：半导体集成电路设备
公开(公告)号：US20050093064A1
公开(公告)日：2005-05-05
申请号：US10779621
申请日：2004-02-18
申请人： Takashi Ohsawa
发明人： Takashi Ohsawa
IPC分类号： H01L21/3205 , H01L21/8242 , H01L23/52 , H01L27/01 , H01L27/02 , H01L27/108 , H01L27/12 , H01L29/786
CPC分类号： H01L27/108 , H01L27/0207 , H01L27/1203 , H01L29/7841 , H01L29/78648
摘要： A semiconductor integrated circuit device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulating layer; source regions of a first conduction type and drain regions of the first conduction type both formed in the semiconductor layer; body regions of a second conduction type formed in the semiconductor layer between the source regions and the drain regions to store data by accumulating or releasing an electric charge; word lines formed on the body regions in electrical isolation from the body regions to extend in a first direction; bit lines connected to the drain regions and extending in a direction different from the first direction; and buried wirings formed in the insulating layer in electrical isolation from the semiconductor substrate and the semiconductor layer, said buried wirings extending in parallel with the bit lines.
摘要翻译：半导体集成电路器件包括半导体衬底; 形成在所述半导体基板上的绝缘层; 通过绝缘层与半导体衬底绝缘的半导体层; 在半导体层中形成第一导电类型的第一导电类型和漏极区的源极区; 形成在源极区域和漏极区域之间的半导体层中的第二导电类型的主体区域，以通过累积或释放电荷来存储数据; 形成在所述主体区域上的与所述主体区域电隔离以在第一方向上延伸的字线; 连接到漏极区并沿与第一方向不同的方向延伸的位线; 以及与半导体衬底和半导体层电隔离形成在绝缘层中的埋入布线，所述埋入布线与位线平行延伸。

76. 发明授权

US06862935B2 Tilt angle measuring apparatus 失效
标题翻译：倾斜角测量仪
公开(公告)号：US06862935B2
公开(公告)日：2005-03-08
申请号：US10670367
申请日：2003-09-26
申请人： Akiharu Fukuda , Takashi Ohsawa
发明人： Akiharu Fukuda , Takashi Ohsawa
IPC分类号： G01B17/00 , G01C9/00 , G01S7/521 , G01S15/02 , G01C9/02 , H04B7/00
CPC分类号： G01C9/00
摘要： A case of tilt angle measuring apparatus is composed of a case body for housing ultrasonic sensors and a cover for covering a top of the case body, and the case body includes a bottom plate having windows for exposing the ultrasonic wave transmitting/receiving faces of the ultrasonic sensors, a side plate extending upward from the peripheral edge of the bottom plate and abutting against the bottom surface of the cover, and horn parts extending downward from the bottom plate so as to surrounding the windows.
摘要翻译：倾斜角测量装置的壳体由用于容纳超声波传感器的壳体和用于覆盖壳体的顶部的盖组成，壳体包括底板，该底板具有用于暴露超声波传感器的超声波发送/接收面的窗口超声波传感器，从底板的周缘向上延伸并抵靠盖的底面的侧板，以及从底板向下延伸以围绕窗户的喇叭部。

77. 发明授权

US06846733B2 Stacked capacitor-type semiconductor storage device and manufacturing method thereof 失效
标题翻译：叠层电容式半导体存储装置及其制造方法
公开(公告)号：US06846733B2
公开(公告)日：2005-01-25
申请号：US10388462
申请日：2003-03-17
申请人： Yusuke Kohyama , Takashi Ohsawa , Shizuo Sawada
发明人： Yusuke Kohyama , Takashi Ohsawa , Shizuo Sawada
IPC分类号： H01L21/28 , H01L21/316 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L21/3205 , H01L21/4763
CPC分类号： H01L27/10888 , H01L21/76831 , H01L21/76834 , H01L21/76897 , H01L27/0207 , H01L27/10852 , H01L27/10855 , H01L27/10885 , H01L2924/0002 , H01L2924/00
摘要： First and second wirings are formed on a first insulating film. Each of the wirings is arranged so that a conductive film, a silicon oxide film and a silicon nitride film are laminated. Thereafter, a silicon oxide insulating film is formed on the whole surface. The silicon oxide insulating film is etched so that a contact hole is formed between the first and second wirings. Since the silicon oxide film and the silicon nitride film exist on the conductive film of each wiring, the conductive film is not exposed at the time of etching. Thereafter, an insulating film is formed on a side wall of the contact hole, and the conductive film exposed through the contact hole is covered by the insulating film.
摘要翻译：第一和第二布线形成在第一绝缘膜上。每个布线被布置成使得导电膜，氧化硅膜和氮化硅膜层压。此后，在整个表面上形成氧化硅绝缘膜。蚀刻氧化硅绝缘膜，使得在第一和第二布线之间形成接触孔。由于在每个布线的导电膜上存在氧化硅膜和氮化硅膜，因此在蚀刻时导电膜不会露出。此后，在接触孔的侧壁上形成绝缘膜，并且通过接触孔露出的导电膜被绝缘膜覆盖。

78. 发明授权

US06803130B1 Composite magnetic material and inductor element 失效
标题翻译：复合磁性材料和电感元件
公开(公告)号：US06803130B1
公开(公告)日：2004-10-12
申请号：US09697542
申请日：2000-10-26
申请人： Kunisaburo Tomono , Takashi Toda , Takashi Ohsawa , Mitsuhiro Fukushima , Hiroshi Marusawa
发明人： Kunisaburo Tomono , Takashi Toda , Takashi Ohsawa , Mitsuhiro Fukushima , Hiroshi Marusawa
IPC分类号： B32B900
CPC分类号： H01F1/37 , H01F1/344 , H01F17/04 , Y10T428/115 , Y10T428/32
摘要： A composite magnetic material comprises a ferrite powder and a resin in which the powder comprises a spinel type ferrite including at least Ni and Co.
摘要翻译：复合磁性材料包括铁氧体粉末和其中粉末包括至少包括Ni和Co的尖晶石型铁氧体的树脂

79. 发明授权

US06567330B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06567330B2
公开(公告)日：2003-05-20
申请号：US10102981
申请日：2002-03-22
申请人： Katsuyuki Fujita , Takashi Ohsawa
发明人： Katsuyuki Fujita , Takashi Ohsawa
IPC分类号： G11C702
CPC分类号： G11C7/06
摘要： A semiconductor memory device has a memory cell array including memory cells; a reference current generating circuit which generates a reference current; a reference voltage generating circuit which generates a reference voltage in a reference node on the basis of the reference current generated by the reference current generating circuit; a first sense circuit which generates an output current on the basis of a cell current of the selected memory cell and which generates a data potential in a sense node on the basis of the output current and the reference current; and a second sense circuit which detects the data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.
摘要翻译：半导体存储器件具有包括存储单元的存储单元阵列; 产生参考电流的参考电流产生电路; 参考电压产生电路，其基于由参考电流产生电路产生的参考电流在参考节点中产生参考电压; 第一感测电路，其基于所选存储单元的单元电流产生输出电流，并且基于输出电流和参考电流在感测节点中产生数据电位; 以及第二感测电路，通过将感测节点中的数据电位与参考节点中的参考电压进行比较来检测保持在所选择的存储器单元中的数据。

80. 发明授权

US06351426B1 DRAM having a power supply voltage lowering circuit 失效
标题翻译： DRAM具有电源电压降低电路
公开(公告)号：US06351426B1
公开(公告)日：2002-02-26
申请号：US09505702
申请日：2000-02-17
申请人： Takashi Ohsawa
发明人： Takashi Ohsawa
IPC分类号： H01L2100
CPC分类号： G11C5/147 , G11C11/4074
摘要： A DRAM includes first to third voltage lowering circuits for lowering a power supply voltage supplied from the exterior and supplying the lowered voltage to an internal circuit. The first voltage lowering circuit is a feedback type circuit for creating a first potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a {overscore (RAS)} signal input buffer, {overscore (CAS)} signal input buffer and {overscore (WE)} signal input buffer. The second voltage lowering circuit is a feedback type circuit is a source follower type circuit for creating a second potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to a VBL generating circuit for generating a bit line precharge potential and a VPL generating circuit for generating a cell plate potential. The third voltage lowering circuit is a source follower type circuit for creating a third potential by lowering the power supply voltage supplied from the exterior and supplying a thus created lowered power supply voltage to all of the other internal circuits except the above circuits.
摘要翻译： DRAM包括用于降低从外部供应的电源电压并将降低的电压提供给内部电路的第一至第三降压电路。第一降压电路是用于通过降低从外部供应的电源电压并将如此产生的降低的电源电压提供给（超芯（RAS））信号输入缓冲器来产生第一电位的反馈型电路，）}信号输入缓冲器和{overscore（WE）}信号输入缓冲器。第二降压电路是反馈型电路，是通过降低从外部供给的电源电压来产生第二电位的源极跟随器电路，并将由此产生的降低的电源电压提供给用于产生位线的VBL产生电路预充电电位和产生电池板电位的VPL产生电路。第三降压电路是用于通过降低从外部供应的电源电压来产生第三电位的源极跟随器电路，并将由此产生的降低的电源电压提供给除了上述电路之外的所有其它内部电路。

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