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71. 发明申请

US20080006854A1 MOSFETS COMPRISING SOURCE/DRAIN REGIONS WITH SLANTED UPPER SURFACES, AND METHOD FOR FABRICATING THE SAME 失效
标题翻译：包含上述上表面的源/漏区域的MOSFETs及其制造方法
公开(公告)号：US20080006854A1
公开(公告)日：2008-01-10
申请号：US11425542
申请日：2006-06-21
申请人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
发明人： Zhijiong Luo , Yung F. Chong , Judson R. Holt , Zhao Lun , Huilong Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： The present invention relates to improved metal-oxide-semiconductor field effect transistor (MOSFET) devices comprising source and drain (S/D) regions having slanted upper surfaces with respect to a substrate surface. Such S/D regions may comprise semiconductor structures that are epitaxially grown in surface recesses in a semiconductor substrate. The surface recesses preferable each has a bottom surface that is parallel to the substrate surface, which is oriented along one of a first set of equivalent crystal planes, and one or more sidewall surfaces that are oriented along a second, different set of equivalent crystal planes. The slanted upper surfaces of the S/D regions function to improve the stress profile in the channel region as well as to reduce contact resistance of the MOSFET. Such S/D regions with slanted upper surfaces can be readily formed by crystallographic etching of the semiconductor substrate, followed by epitaxial growth of a semiconductor material.
摘要翻译：本发明涉及包括源极和漏极（S / D）区域的改进的金属氧化物半导体场效应晶体管（MOSFET）器件，其具有相对于衬底表面倾斜的上表面。这样的S / D区域可以包括在半导体衬底中的表面凹槽中外延生长的半导体结构。优选的表面凹部具有平行于基板表面的底表面，该底表面沿着第一组等效晶面中的一个取向，并且沿着第二不同组的等效晶面定向的一个或多个侧壁表面。 S / D区域的倾斜上表面用于改善沟道区域中的应力分布以及降低MOSFET的接触电阻。具有倾斜的上表面的这种S / D区域可以容易地通过半导体衬底的晶体蚀刻形成，随后半导体材料的外延生长。

72. 发明申请

US20070275510A1 METAL OXIDE FIELD EFFECT TRANSISTOR WITH A SHARP HALO AND A METHOD OF FORMING THE TRANSISTOR 有权
标题翻译：具有夏普HALO的金属氧化物场效应晶体管和形成晶体管的方法
公开(公告)号：US20070275510A1
公开(公告)日：2007-11-29
申请号：US11420318
申请日：2006-05-25
申请人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
发明人： Huajie Chen , Judson R. Holt , Rangarajan Jagannathan , Wesley C. Natzle , Michael R. Sievers , Richard S. Wise
IPC分类号： H01L21/8232 , H01L21/8234 , H01L21/335
CPC分类号： H01L29/66636 , H01L29/6659 , H01L29/7833
摘要： Disclosed are embodiments of a MOSFET with defined halos that are bound to defined source/drain extensions and a method of forming the MOSFET. A semiconductor layer is etched to form recesses that undercut a gate dielectric layer. A low energy implant forms halos. Then, a COR pre-clean is performed and the recesses are filled by epitaxial deposition. The epi can be in-situ doped or subsequently implanted to form source/drain extensions. Alternatively, the etch is immediately followed by the COR pre-clean, which is followed by epitaxial deposition to fill the recesses. During the epitaxial deposition process, the deposited material is doped to form in-situ doped halos and, then, the dopant is switched to form in-situ doped source/drain extensions adjacent to the halos. Alternatively, after the in-situ doped halos are formed the deposition process is performed without dopants and an implant is used to form source/drain extensions.
摘要翻译：公开了具有限定的限定的卤素的MOSFET的实施例，其限定的源极/漏极扩展部分以及形成MOSFET的方法。蚀刻半导体层以形成切割栅极介电层的凹部。低能量植入物形成晕轮。然后，执行COR预清洁，并且通过外延沉积填充凹部。外延可以被原位掺杂或随后植入以形成源/漏扩展。或者，蚀刻之后紧接着是COR预清洁，随后进行外延沉积以填充凹部。在外延沉积工艺期间，沉积的材料被掺杂以形成原位掺杂的光晕，然后切换掺杂剂以形成邻近光晕的原位掺杂的源极/漏极延伸。或者，在形成原位掺杂的光晕之后，进行沉积工艺而没有掺杂剂，并且使用注入来形成源极/漏极延伸部。

73. 发明授权

US09006052B2 Self aligned device with enhanced stress and methods of manufacture 有权
标题翻译：具有增强应力和制造方法的自对准装置
公开(公告)号：US09006052B2
公开(公告)日：2015-04-14
申请号：US12901733
申请日：2010-10-11
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L21/00 , H01L29/786 , H01L29/66 , H01L29/78
CPC分类号： H01L29/78654 , H01L29/66553 , H01L29/66651 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method includes forming a stressed Si layer in a trench formed in a stress layer deposited on a substrate. The stressed Si layer forms an active channel region of a device. The method further includes forming a gate structure in the active channel region formed from the stressed Si layer.
摘要翻译：一种方法包括在沉积在基底上的应力层中形成的沟槽中形成应力Si层。受应力的Si层形成器件的有源沟道区。该方法还包括在由应力Si层形成的有源沟道区中形成栅极结构。

74. 发明授权

US08716037B2 Measurement of CMOS device channel strain by X-ray diffraction 失效
$Measurement of CMOS device channel strain by X-ray diffraction$
标题翻译：通过X射线衍射测量CMOS器件通道应变
公开(公告)号：US08716037B2
公开(公告)日：2014-05-06
申请号：US12967323
申请日：2010-12-14
申请人： Thomas N. Adam , Stephen W. Bedell , Eric C. Harley , Judson R. Holt , Anita Madan , Conal E. Murray , Teresa L. Pinto
发明人： Thomas N. Adam , Stephen W. Bedell , Eric C. Harley , Judson R. Holt , Anita Madan , Conal E. Murray , Teresa L. Pinto
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L29/1054 , G01N23/207 , G01N2223/607 , G01N2223/6116 , H01L21/823807 , H01L22/12
摘要： A direct measurement of lattice spacing by X-ray diffraction is performed on a periodic array of unit structures provided on a substrate including semiconductor devices. Each unit structure includes a single crystalline strained material region and at least one stress-generating material region. For example, the single crystalline strained material region may be a structure simulating a channel of a field effect transistor, and the at least one stress-generating material region may be a single crystalline semiconductor region in epitaxial alignment with the single crystalline strained material region. The direct measurement can be performed in-situ at various processing states to provide in-line monitoring of the strain in field effect transistors in actual semiconductor devices.
摘要翻译：在包括半导体器件的衬底上提供的单元结构的周期性阵列上进行通过X射线衍射的晶格间距的直接测量。每个单位结构包括单晶应变材料区域和至少一个应力产生材料区域。例如，单晶应变材料区域可以是模拟场效应晶体管的沟道的结构，并且所述至少一个应力产生材料区域可以是与单晶应变材料区域外延对准的单晶半导体区域。可以在各种处理状态下原位执行直接测量，以提供在实际半导体器件中场效应晶体管中的应变的在线监测。

75. 发明授权

US08513718B2 Stress enhanced transistor devices and methods of making 失效
标题翻译：应力增强晶体管器件和制造方法
公开(公告)号：US08513718B2
公开(公告)日：2013-08-20
申请号：US13419164
申请日：2012-03-13
申请人： Johnathan E. Faltermeier , Judson R. Holt , Xuefeng Hua
发明人： Johnathan E. Faltermeier , Judson R. Holt , Xuefeng Hua
IPC分类号： H01L29/76
CPC分类号： H01L29/7849 , H01L29/66636 , H01L29/78
摘要： A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
摘要翻译：晶体管器件包括通过栅极电介质在半导体衬底上间隔开的栅极导体，其中半导体衬底包括位于栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中该沟道区域包括栅极下方的底切区域导体; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。

76. 发明授权

US08299535B2 Delta monolayer dopants epitaxy for embedded source/drain silicide 有权
标题翻译：用于嵌入式源极/漏极硅化物的三角形单层掺杂剂外延
公开(公告)号：US08299535B2
公开(公告)日：2012-10-30
申请号：US12823163
申请日：2010-06-25
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jeffrey B. Johnson , Jinghong Li , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jeffrey B. Johnson , Jinghong Li , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L29/78 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/66636 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7834 , H01L29/7848
摘要： Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer.
摘要翻译：公开了在其中具有嵌入的应力元件的半导体结构。所公开的结构包括位于半导体衬底的上表面上的至少一个FET栅极堆叠。所述至少一个FET栅极堆叠包括在所述至少一个FET栅极堆叠中的覆盖区域处位于所述半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。该结构还包括位于至少一个FET栅极堆叠的相对侧上并且位于半导体衬底内的嵌入式应力元件。每个嵌入式应力元件包括从底部到顶部的第一外延掺杂半导体材料的第一层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变;第二层位于第一层顶部的第二外延掺杂半导体材料和位于第二层的上表面上的掺杂剂的Δ单层。该结构还包括直接位于三角形单层的上表面上的金属半导体合金触点。

77. 发明申请

US20120261717A1 MONOLAYER DOPANT EMBEDDED STRESSOR FOR ADVANCED CMOS 有权
标题翻译：用于高级CMOS的单层掺杂嵌入式压电器
公开(公告)号：US20120261717A1
公开(公告)日：2012-10-18
申请号：US13533499
申请日：2012-06-26
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L27/092
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
摘要翻译：公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

78. 发明申请

US20120228716A1 METHODS OF INTEGRATING REVERSE eSiGe ON NFET AND SiGe CHANNEL ON PFET, AND RELATED STRUCTURE 审中-公开
标题翻译：将NFET和SiGe通道上的反向电流集成在PFET上的方法及相关结构
公开(公告)号：US20120228716A1
公开(公告)日：2012-09-13
申请号：US13478400
申请日：2012-05-23
申请人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
发明人： Eric C. T. Harley , Judson R. Holt , Dominic J. Schepis , Michael D. Steigerwalt , Linda Black , Rick Carter
IPC分类号： H01L27/092
CPC分类号： H01L21/823814 , H01L21/823807 , H01L29/1054 , H01L29/161 , H01L29/66636 , H01L29/7848
摘要： A structure including an NFET having an embedded silicon germanium (SiGe) plug in a channel of the NFET; a PFET having a SiGe channel; and a trench isolation between the NFET and the PFET, wherein the NFET and the PFET are devoid of SiGe epitaxial growth edge effects.
摘要翻译：包括在NFET的沟道中具有嵌入硅锗（SiGe）插头的NFET的结构; 具有SiGe沟道的PFET; 以及在NFET和PFET之间的沟槽隔离，其中NFET和PFET没有SiGe外延生长边缘效应。

79. 发明申请

US20120181578A1 PRE-GATE, SOURCE/DRAIN STRAIN LAYER FORMATION 审中-公开
标题翻译：前馈，源/排水应变层形成
公开(公告)号：US20120181578A1
公开(公告)日：2012-07-19
申请号：US13432018
申请日：2012-03-28
申请人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
发明人： Judson R. Holt , Viorel C. Ontalus , Keith H. Tabakman
IPC分类号： H01L29/78
CPC分类号： H01L29/7848 , H01L21/823412 , H01L29/66477 , H01L29/78 , H01L29/7842 , H01L29/7849
摘要： A method produces a transistor. The method forms a strain-producing layer on a base layer and then removes at least one portion of the strain-producing layer to create at least one opening in the strain-producing layer. This leaves first and second portions of the strain-producing layer on the substrate. The first and second portions of the strain-producing layer comprise source and drain stressor regions of the transistor. The method then grows a channel region in the opening of the strain-producing layer from the base layer, forms a gate insulator on the channel region, and forms a gate conductor on the gate insulator.
摘要翻译：一种方法产生晶体管。该方法在基层上形成应变产生层，然后去除应变产生层的至少一部分以在应变产生层中产生至少一个开口。这使得在基片上产生应变的层的第一和第二部分。应变产生层的第一和第二部分包括晶体管的源极和漏极应力区域。然后，该方法从基底层在应变产生层的开口中生长通道区域，在沟道区上形成栅极绝缘体，并在栅极绝缘体上形成栅极导体。

80. 发明申请

US20120104507A1 METHOD FOR GROWING STRAIN-INDUCING MATERIALS IN CMOS CIRCUITS IN A GATE FIRST FLOW 有权
标题翻译：在门电路第一流程中生长应变诱导材料的方法
公开(公告)号：US20120104507A1
公开(公告)日：2012-05-03
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

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