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71. 发明授权

US09082657B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US09082657B2
公开(公告)日：2015-07-14
申请号：US13676672
申请日：2012-11-14
申请人： Chih-Wei Hu , Teng-Hao Yeh , Yen-Hao Shih
发明人： Chih-Wei Hu , Teng-Hao Yeh , Yen-Hao Shih
IPC分类号： H01L21/3205 , H01L27/115
CPC分类号： H01L27/11578 , H01L21/28575 , H01L27/11565 , H01L29/0891 , H01L29/2003 , H01L29/42316 , H01L29/42376 , H01L29/452 , H01L29/66462 , H01L29/7787
摘要： A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. Semiconductor units are arranged on a substrate. A material layer is formed on the semiconductor units. A first patterned mask layer is formed on the semiconductor units. The first patterned mask layer has a mask opening corresponding to a portion of the semiconductor units and exposing the material layer. A portion of the material layer exposed by the mask opening is removed to remain a portion of the material layer on a sidewall of each of the semiconductor units exposed by the mask opening to form spacer structures.
摘要翻译：提供半导体结构及其制造方法。该方法包括以下步骤。半导体单元布置在基板上。在半导体单元上形成材料层。在半导体单元上形成第一图案化掩模层。第一图案化掩模层具有对应于半导体单元的一部分并且暴露材料层的掩模开口。去除由掩模开口暴露的材料层的一部分，以保留由掩模开口暴露的每个半导体单元的侧壁上的材料层的一部分，以形成间隔结构。

72. 发明授权

US09082656B2 NAND flash with non-trapping switch transistors 有权
标题翻译： NAND闪存与非陷阱开关晶体管
公开(公告)号：US09082656B2
公开(公告)日：2015-07-14
申请号：US13294852
申请日：2011-11-11
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L27/115
CPC分类号： H01L27/1157 , H01L27/11578
摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.
摘要翻译：一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。然后形成字线和选择线。介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

73. 发明授权

US08951862B2 Damascene word line 有权
标题翻译：大马士革字线
公开(公告)号：US08951862B2
公开(公告)日：2015-02-10
申请号：US13347331
申请日：2012-01-10
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L21/336
CPC分类号： H01L27/11582 , H01L29/7926
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。诸如硅的导电线形成在堆叠的非易失性存储器结构之上。字线沟槽分离出相邻的硅线。由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。字线是在字线沟中制作的。

74. 发明授权

US08846549B2 Method of forming bottom oxide for nitride flash memory 有权
标题翻译：形成氮化物闪存底部氧化物的方法
公开(公告)号：US08846549B2
公开(公告)日：2014-09-30
申请号：US11235786
申请日：2005-09-27
申请人： Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/31 , G11C16/04 , H01L21/28 , H01L29/51
CPC分类号： H01L21/28282 , G11C16/0466 , H01L29/513
摘要： A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.
摘要翻译：半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。底部氧化物层可以具有高达5E19cm-3的氢浓度和高达5E11cm-2eV-1的界面陷阱密度。三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。

75. 发明申请

US20130334575A1 Damascene Word Line 有权
标题翻译：大马士革字线
公开(公告)号：US20130334575A1
公开(公告)日：2013-12-19
申请号：US13527259
申请日：2012-06-19
申请人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
发明人： Shih-Hung Chen , Yen-Hao Shih , Hang-Ting Lue
IPC分类号： H01L27/10 , H01L21/768
CPC分类号： H01L27/11578 , H01L27/11565
摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.
摘要翻译：该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

76. 发明申请

US20130214340A1 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD OF THE SAME 有权
标题翻译：其半导体结构及其制造方法
公开(公告)号：US20130214340A1
公开(公告)日：2013-08-22
申请号：US13401634
申请日：2012-02-21
申请人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
发明人： Shih-Hung Chen , Hang-Ting Lue , Yen-Hao Shih
IPC分类号： H01L29/68 , H01L21/283
CPC分类号： H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11578 , H01L29/7881 , H01L29/792
摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, and a first conductive layer. The first stacked structure is formed on the substrate and includes a conductive structure and an insulating structure, and the conductive structure is disposed adjacent to the insulating structure. The first conductive layer is formed on the substrate and surrounds two side walls and a part of the top portion of the first stacked structure for exposing a portion of the first stacked structure.
摘要翻译：提供了一种半导体结构及其制造方法。半导体结构包括基板，第一堆叠结构和第一导电层。第一堆叠结构形成在基板上，并且包括导电结构和绝缘结构，并且导电结构邻近于绝缘结构设置。第一导电层形成在基板上并且包围第一层叠结构的两个侧壁和顶部的一部分，用于暴露第一堆叠结构的一部分。

77. 发明授权

US08183618B2 Method for fabricating a charge trapping memory device 有权
标题翻译：电荷俘获存储器件的制造方法
公开(公告)号：US08183618B2
公开(公告)日：2012-05-22
申请号：US12962361
申请日：2010-12-07
申请人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
发明人： Yen-Hao Shih , Chi-Pin Lu , Jung-Yu Hsieh
IPC分类号： H01L29/76
CPC分类号： H01L21/28282
摘要： A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.
摘要翻译：一种制造电荷俘获存储器件的方法包括：提供衬底; 在所述基板上形成第一氧化物层; 在衬底中形成多个BD区域; 通过工艺对第一氧化物层和衬底的界面进行氮化; 在所述第一氧化物层上形成电荷捕获层; 以及在电荷俘获层上形成第二氧化物层。

78. 发明授权

US08059449B2 Phase change device having two or more substantial amorphous regions in high resistance state 有权
标题翻译：具有两个或多个具有高电阻状态的实质非晶区域的相变装置
公开(公告)号：US08059449B2
公开(公告)日：2011-11-15
申请号：US12717850
申请日：2010-03-04
申请人： Yen-Hao Shih , Chieh-Fang Chen , Hsiang-Lan Lung
发明人： Yen-Hao Shih , Chieh-Fang Chen , Hsiang-Lan Lung
IPC分类号： G11C11/00
CPC分类号： H01L45/126 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： Memory devices are described herein along with method for operating the memory device. A memory cell as described herein includes a first electrode and a second electrode. The memory cell also comprises phase change material having first and second active regions arranged in series along an inter-electrode current path between the first and second electrode.
摘要翻译：这里描述了存储器件以及用于操作存储器件的方法。如本文所述的存储单元包括第一电极和第二电极。存储单元还包括具有沿第一和第二电极之间的电极间电流路径串联布置的第一和第二有源区的相变材料。

79. 发明授权

US08022465B2 Low hydrogen concentration charge-trapping layer structures for non-volatile memory 有权
标题翻译：用于非易失性存储器的低氢浓度电荷捕获层结构
公开(公告)号：US08022465B2
公开(公告)日：2011-09-20
申请号：US11274781
申请日：2005-11-15
申请人： Yen-Hao Shih , Min-Ta Wu , Shin-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Yen-Hao Shih , Min-Ta Wu , Shin-Chin Lee , Jung-Yu Hsieh , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/518
摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.
摘要翻译：存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

80. 发明授权

US07977227B2 Method of manufacturing a non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07977227B2
公开(公告)日：2011-07-12
申请号：US12216679
申请日：2008-07-09
申请人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
发明人： Chiahua Ho , Yen-Hao Shih , Hang-Ting Lue , Erh-Kun Lai , Kuang Yeu Hsieh
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115
摘要： A method of manufacturing a non-volatile semiconductor memory device includes forming a sub-gate without an additional mask. A low word-line resistance is formed by a metal silicide layer on a main gate of the memory device. In operation, application of a voltage to the sub-gate forms a transient state inversion layer that serves as a bit-line, so that no implantation is required to form the bit-line.
摘要翻译：一种制造非易失性半导体存储器件的方法包括在没有附加掩模的情况下形成子栅极。低字线电阻由存储器件的主栅极上的金属硅化物层形成。在操作中，向子栅极施加电压形成用作位线的瞬态状态反转层，从而不需要植入来形成位线。

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