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71. 发明授权

US07249339B1 Method and apparatus for optimizing delay paths through field programmable gate arrays 有权
标题翻译：用于通过现场可编程门阵列优化延迟路径的方法和装置
公开(公告)号：US07249339B1
公开(公告)日：2007-07-24
申请号：US10918974
申请日：2004-08-16
申请人： Bruce Pedersen
发明人： Bruce Pedersen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5031
摘要： A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.
摘要翻译：用于改进现场可编程门阵列（FPGA）设计的方法包括响应于FPGA上的节点的输入的单一特性以及馈送输入的节点的上升和下降延迟来修改设计。

72. 发明授权

US07129745B2 Apparatus and methods for adjusting performance of integrated circuits 有权
公开(公告)号：US07129745B2
公开(公告)日：2006-10-31
申请号：US10865402
申请日：2004-06-10
申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
发明人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
IPC分类号： H03K19/173
CPC分类号： G06F17/5054 , H03K5/133 , H03K19/00369 , H03K2005/00058 , H03K2005/00156 , H03K2217/0018
摘要： A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

73. 发明授权

US07100141B1 Technology mapping technique for fracturable logic elements 有权
$Technology mapping technique for fracturable logic elements$
标题翻译：可分割逻辑元件的技术映射技术
公开(公告)号：US07100141B1
公开(公告)日：2006-08-29
申请号：US10745913
申请日：2003-12-23
申请人： Boris Ratchev , Yean-Yow Hwang , Bruce Pedersen
发明人： Boris Ratchev , Yean-Yow Hwang , Bruce Pedersen
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.
摘要翻译：通过在可编程逻辑计算机辅助设计流程的技术映射阶段中使用“平衡”来最小化具有可分解逻辑元件的可编程逻辑电路面积的技术。可破碎的LE可以用于许多方式的逻辑实现，例如用作一个最大尺寸的查找表（LUT）或多个较小的LUT。可以共享多个较小LUT的更多输入中的一个。通过平衡，这意味着技术映射算法被调整为使用更小的LUT和更少的最大尺寸的LUT来实现电路。虽然这是违反直觉的，因为较大的LUT在吸收栅极方面更有效，但是该技术通过将小型LUT封装成可分裂的LE来实现较小的最终电路面积。

74. 发明授权

US06995590B1 Hybrid phase/delay locked loop circuits and methods 失效
标题翻译：混合相位/延迟锁定环路电路及方法
公开(公告)号：US06995590B1
公开(公告)日：2006-02-07
申请号：US10668447
申请日：2003-09-22
申请人： Bruce Pedersen
发明人： Bruce Pedersen
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/083 , H03L7/0995 , H03L7/18
摘要： A circuit is provided that aligns the phase of a delay signal with an input clock signal. The circuit functions as a phase locked loop (PLL) in a first state of operation and as a delay locked loop (DLL) in a second state of operation. An adjustable delay circuit generates the delay signal. A phase detector compares the input clock signal to the delay signal to generate a phase detection signal. The adjustable delay circuit adjusts the phase of the delay signal in response to the phase detection signal. A multiplexer couples the delay signal back to the input of the adjustable delay circuit using a feedback loop in the first state of operation. The multiplexer couples the input clock signal to the input of the adjustable delay circuit in the second state of operation.
摘要翻译：提供了将延迟信号的相位与输入时钟信号对准的电路。该电路作为处于第一操作状态的锁相环（PLL）和在第二操作状态下作为延迟锁定环（DLL）起作用。可调延迟电路产生延迟信号。相位检测器将输入时钟信号与延迟信号进行比较以产生相位检测信号。可调节延迟电路根据相位检测信号调整延迟信号的相位。多路复用器使用第一操作状态的反馈回路将延迟信号耦合回可调节延迟电路的输入端。在第二操作状态下，多路复用器将输入时钟信号耦合到可调延迟电路的输入。

75. 发明授权

US06888373B2 Fracturable incomplete look up table for area efficient logic elements 有权
标题翻译：用于区域高效逻辑元素的难以置信的不完整查询表
公开(公告)号：US06888373B2
公开(公告)日：2005-05-03
申请号：US10365647
申请日：2003-02-11
申请人： Sinan Kaptanoglu , David Lewis , Bruce Pedersen
发明人： Sinan Kaptanoglu , David Lewis , Bruce Pedersen
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728
摘要： Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.
摘要翻译：公开了一种可配置逻辑电路，其包括至少6个输入和至少两个输出。可配置逻辑元件只能执行所有6输入逻辑功能的一个子集，因此需要比可执行所有6输入逻辑功能的6-LUT更小的硅面积。而且，可配置逻辑电路可被配置为使得输入的第一子集驱动输出之一，并且输入的第二子集驱动另一输出。

76. 发明授权

US06490717B1 Generation of sub-netlists for use in incremental compilation 有权
标题翻译：生成用于增量编译的子网表
公开(公告)号：US06490717B1
公开(公告)日：2002-12-03
申请号：US09639657
申请日：2000-08-15
申请人： Bruce Pedersen , Francis B. Heile , Marwan Adel Khalaf , David Wolk Mendel
发明人： Bruce Pedersen , Francis B. Heile , Marwan Adel Khalaf , David Wolk Mendel
IPC分类号： G06F1750
CPC分类号： G06F8/60 , G01R31/3177 , G01R31/318516 , G06F8/65 , G06F8/71 , G06F11/0748 , G06F11/2294 , G06F17/5022 , G06F17/5027 , G06F17/5045 , G06F17/5054 , G06F2217/04 , G06Q10/06 , G06Q10/10 , Y10S707/99953 , Y10S707/99954
摘要： A technique is disclosed for performing an incremental recompile of an electronic design that has been previous compiled and then changed by a designer. This is accomplished by identifying a “sub-netlist” within the larger netlist of the changed design. The sub-netlist contains the sphere of influence of the designer's changes to the original design. During incremental recompile, only the sub-netlist is compiled; the remainder of the netlist is left as is from the previous compile. After the sub-netlist is synthesized, it is integrated back into the synthesized netlist from the previous compilation. The newly synthesized netlist for the changed design is mapped to logic cells which are then fit onto a target hardware device.
摘要翻译：公开了一种用于执行先前编译然后由设计者改变的电子设计的增量重新编译的技术。这是通过在更改的设计的较大网表中识别“子网表”来实现的。子网表包含设计师对原始设计的变化的影响范围。在增量重新编译期间，仅编制子网表; 网表的剩余部分与以前的编译一样。子网表合成后，从以前的编译中集成回合成的网表。用于改变后的设计的新合成的网表被映射到逻辑单元，然后将其合并到目标硬件设备上。

77. 发明授权

US06249149B1 Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device 失效
标题翻译：用于集中生成用于可编程逻辑器件的逻辑阵列块的使能时钟信号的装置和方法
公开(公告)号：US06249149B1
公开(公告)日：2001-06-19
申请号：US09012682
申请日：1998-01-23
申请人： Bruce Pedersen
发明人： Bruce Pedersen
IPC分类号： H03K1900
CPC分类号： G06F1/10
摘要： A logic array block of a programmable logic device includes a clock generation circuit. The clock generation circuit has an input node to receive a clock signal, an enable signal input node to receive an enable signal, a clock generation circuit output node, and a digital logic circuit connected between the clock generation circuit input node, the enable signal input node, and the clock generation circuit output node. The digital logic circuit generates an enabled clock signal on the clock generation circuit output node in response to the clock signal and the enable signal when the enable signal has been asserted during a previous clock state of the clock signal. A set of logic elements, each of which includes a logic element clock input node, is connected to the clock generation circuit output node such that each logic element of the set of logic elements receives the enabled clock signal from the clock generation circuit.
摘要翻译：可编程逻辑器件的逻辑阵列块包括时钟产生电路。时钟发生电路具有接收时钟信号的输入节点，接收使能信号的使能信号输入节点，时钟产生电路输出节点和连接在时钟发生电路输入节点之间的数字逻辑电路，使能信号输入节点和时钟生成电路输出节点。数字逻辑电路响应于时钟信号和使能信号在时钟信号的先前时钟状态中被使能信号被置位而在时钟产生电路输出节点上产生使能的时钟信号。一组逻辑元件，每个逻辑元件包括逻辑元件时钟输入节点，连接到时钟产生电路输出节点，使得该组逻辑元件的每个逻辑元件从时钟产生电路接收使能的时钟信号。

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