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71. 发明授权

US5766803A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
公开(公告)号：US5766803A
公开(公告)日：1998-06-16
申请号：US659165
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , G03F9/00
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

72. 发明授权

US5733798A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
公开(公告)号：US5733798A
公开(公告)日：1998-03-31
申请号：US655247
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

73. 发明授权

US5717242A Integrated circuit having local interconnect for reduing signal cross coupled noise 失效
公开(公告)号：US5717242A
公开(公告)日：1998-02-10
申请号：US633473
申请日：1996-04-17
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

74. 发明授权

US06376330B1 Dielectric having an air gap formed between closely spaced interconnect lines 失效
标题翻译：电介质具有形成在紧密间隔的互连线之间的气隙
公开(公告)号：US06376330B1
公开(公告)日：2002-04-23
申请号：US08655242
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.
摘要翻译：提供一种电介质材料，其具有在电介质中有目的地形成的气隙。电介质被沉积，并且在相应的互连线之间形成气隙。有意地控制互连线之间的几何形状以实现在电介质CVD期间产生气隙所需的大的纵横比。互连之间存在空隙，以减少线间电容，从而减少与紧密间隔的互连相关的传播延迟。

75. 发明授权

US6127719A Subfield conductive layer and method of manufacture 失效
标题翻译：子场导电层及其制造方法
公开(公告)号：US6127719A
公开(公告)日：2000-10-03
申请号：US038464
申请日：1998-03-11
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L29/00 , H01L31/119
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

76. 发明授权

US6043544A Semiconductor gate conductor with a substantially uniform doping profile having minimal susceptibility to dopant penetration into the underlying gate dielectric 有权
标题翻译：具有基本上均匀的掺杂分布的半导体栅极导体对掺杂剂渗透到下面的栅极电介质中具有最小的敏感性
公开(公告)号：US6043544A
公开(公告)日：2000-03-28
申请号：US140202
申请日：1998-08-26
申请人： Mark W. Michael , Robert Dawson
发明人： Mark W. Michael , Robert Dawson
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/76
CPC分类号： H01L21/28035 , H01L21/823842
摘要： A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioning is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied. Slow diffusers are initially placed closer to the bottom surface of the polysilicon, since they do not diffuse as readily. The source and drain regions are implanted using a very low energy implant, separately from the polysilicon implants, to produce a desirable shallow source and drain region within the semiconductor substrate.
摘要翻译：提出了一种半导体制造工艺，其优化栅极导体内杂质的位置，栅极导体中跨越栅极导体的源极/漏极。通过使用不同能量的单独注入来取决于栅极导体是指PMOS还是NMOS晶体管来实现最佳定位。用于形成栅极导体的多晶硅层在图案化之前被掺杂，使得源极和漏极区域受到保护。当植入诸如硼的快速扩散器时执行低能量注入，并且当植入像砷这样的慢扩散器时执行高能量注入。这使得在施加热循环之后，杂质在整个栅极导体横截面中的最佳定位。最初放置快速扩散器远离多晶硅的底表面，并在加热时在多晶硅的底表面附近扩散。缓慢扩散器最初放置得更靠近多晶硅的底表面，因为它们不会容易地扩散。使用与多晶硅植入物分开的非常低能量的注入来注入源极区和漏极区，以在半导体衬底内产生期望的浅源极和漏极区。

77. 发明授权

US5968843A Method of planarizing a semiconductor topography using multiple polish pads 失效
标题翻译：使用多个抛光垫平面化半导体形貌的方法
公开(公告)号：US5968843A
公开(公告)日：1999-10-19
申请号：US768278
申请日：1996-12-18
申请人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： Robert Dawson , H. Jim Fulford, Jr. , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/302
CPC分类号： H01L21/31053
摘要： An improved method for planarizing an interlevel dielectric comprising two chemical mechanical polish steps. After an interlevel dielectric containing a topographical valley between a pair of topographical peaks is formed, the dielectric is chemically-mechanically polished in a first polish step at a first force using a first polish pad having a first rigidity to round the sharp dielectric corners or edges that exist at the transition between the peaks and valleys. After the first polish step has rounded the edges, a second polish step is performed with a second polish pad of second rigidity. The second polish pad is more rigid than the first polish pad and the second force is greater than the first. The second polish steps uses a high viscosity slurry to reduce slurry turnover in the regions proximate to the dielectric valleys thereby reducing the chemical etching in the valleys and improving the planarization efficiency.
摘要翻译：一种用于平坦化层间电介质的改进方法，包括两个化学机械抛光步骤。在形成包含一对形貌峰之间的形貌谷的层间电介质之后，使用具有第一刚性的第一抛光垫在第一抛光步骤中以第一力进行化学机械抛光的电介质以使尖锐的电介质拐角或边缘存在于峰谷之间的过渡处。在第一抛光步骤使边缘变圆之后，用第二刚性的第二抛光垫进行第二抛光步骤。第二抛光垫比第一抛光垫更刚性，第二抛光垫大于第一抛光垫。第二抛光步骤使用高粘度浆料来减少靠近电介质谷的区域中的浆料周转，从而减少了谷中的化学蚀刻并提高了平坦化效率。

78. 发明授权

US5963803A Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths 失效
标题翻译：制造具有不同栅极厚度和间隔宽度的N沟道和P沟道IGFET的方法
公开(公告)号：US5963803A
公开(公告)日：1999-10-05
申请号：US17254
申请日：1998-02-02
申请人： Robert Dawson , Mark W. Michael , Charles E. May
发明人： Robert Dawson , Mark W. Michael , Charles E. May
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/02
CPC分类号： H01L21/82385 , H01L21/823864 , H01L27/0922
摘要： A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region. Preferably, the N-channel device is formed in the first active region, the P-channel device is formed in the second active region, and the N-channel and P-channel devices include lightly and heavily doped source and drain regions. In this manner, the relatively thick gate for the P-channel device reduces boron penetration, and the relatively wide spacers for the P-channel device offset the rapid diffusion of boron in the heavily doped source and drain regions of the P-channel device during high temperature processing so that the lightly doped source and drain regions for the N-channel and P-channel devices have the desired sizes.
摘要翻译：公开了一种制造具有不同栅极厚度和间隔物宽度的N沟道和P沟道IGFET的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，其中第二有源区栅极具有比第一栅极大得多的厚度，在第二栅极的相对侧壁附近形成第一间隔物，其紧邻第一栅极的相对侧壁和第二间隔物，其中第二间隔物具有比第一栅极大得多的宽度由于第二栅极具有比第一栅极大得多的厚度的间隔物，以及在第一有源区中形成第二导电类型的第一源极和第一漏极，以及在第一有源区中形成第一导电类型的第二源极和第二漏极第二活跃区域。优选地，N沟道器件形成在第一有源区中，P沟道器件形成在第二有源区中，并且N沟道和P沟道器件包括轻掺杂和重掺杂的源极和漏极区。以这种方式，用于P沟道器件的相对较厚的栅极减少硼渗透，并且用于P沟道器件的相对较宽的间隔物抵消P沟道器件的重掺杂源极和漏极区域中硼的快速扩散，高温处理使得用于N沟道和P沟道器件的轻掺杂源极和漏极区域具有期望的尺寸。

79. 发明授权

US5783864A Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
公开(公告)号：US5783864A
公开(公告)日：1998-07-21
申请号：US655248
申请日：1996-06-05
申请人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/522 , H01L29/41
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.

80. 发明授权

US5767000A Method of manufacturing subfield conductive layer 失效
标题翻译：制造子场导电层的方法
公开(公告)号：US5767000A
公开(公告)日：1998-06-16
申请号：US655243
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L21/76
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

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