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1. 发明授权

US5963803A Method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths 失效
标题翻译：制造具有不同栅极厚度和间隔宽度的N沟道和P沟道IGFET的方法
公开(公告)号：US5963803A
公开(公告)日：1999-10-05
申请号：US17254
申请日：1998-02-02
申请人： Robert Dawson , Mark W. Michael , Charles E. May
发明人： Robert Dawson , Mark W. Michael , Charles E. May
IPC分类号： H01L21/8238 , H01L27/092 , H01L27/02
CPC分类号： H01L21/82385 , H01L21/823864 , H01L27/0922
摘要： A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region. Preferably, the N-channel device is formed in the first active region, the P-channel device is formed in the second active region, and the N-channel and P-channel devices include lightly and heavily doped source and drain regions. In this manner, the relatively thick gate for the P-channel device reduces boron penetration, and the relatively wide spacers for the P-channel device offset the rapid diffusion of boron in the heavily doped source and drain regions of the P-channel device during high temperature processing so that the lightly doped source and drain regions for the N-channel and P-channel devices have the desired sizes.
摘要翻译：公开了一种制造具有不同栅极厚度和间隔物宽度的N沟道和P沟道IGFET的方法。该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，其中第二有源区栅极具有比第一栅极大得多的厚度，在第二栅极的相对侧壁附近形成第一间隔物，其紧邻第一栅极的相对侧壁和第二间隔物，其中第二间隔物具有比第一栅极大得多的宽度由于第二栅极具有比第一栅极大得多的厚度的间隔物，以及在第一有源区中形成第二导电类型的第一源极和第一漏极，以及在第一有源区中形成第一导电类型的第二源极和第二漏极第二活跃区域。优选地，N沟道器件形成在第一有源区中，P沟道器件形成在第二有源区中，并且N沟道和P沟道器件包括轻掺杂和重掺杂的源极和漏极区。以这种方式，用于P沟道器件的相对较厚的栅极减少硼渗透，并且用于P沟道器件的相对较宽的间隔物抵消P沟道器件的重掺杂源极和漏极区域中硼的快速扩散，高温处理使得用于N沟道和P沟道器件的轻掺杂源极和漏极区域具有期望的尺寸。

2. 发明授权

US5913106A Method for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques 失效
标题翻译：使用浅沟槽和再填充技术制造的含水装置的接头泄漏检测方法
公开(公告)号：US5913106A
公开(公告)日：1999-06-15
申请号：US46974
申请日：1998-03-24
申请人： Frederick N. Hause , Charles E. May , Robert Dawson
发明人： Frederick N. Hause , Charles E. May , Robert Dawson
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002
摘要： A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.
摘要翻译：在浅沟槽隔离装置连接处使用电阻保护掩模，以覆盖设备区域外围的条带之外的设备区域。在器件的中心表面部分上形成的硅化物层和在其上防止硅化物形成的器件的周边上的条带区域形成用于评估结合形成的测试结构，其免于在器件沟槽上的硅化物形成的影响侧壁。将测试结构上的电气测试和泄漏测量直接与类似的硅化物浅沟槽隔离器件进行比较，这些器件不包含电阻器保护掩模和没有硅化物的浅沟槽隔离器件，以确定自对准处理是否包括结漏现象和短路电路

3. 发明授权

US5714392A Rapid thermal anneal system and method including improved temperature sensing and monitoring 失效
公开(公告)号：US5714392A
公开(公告)日：1998-02-03
申请号：US687857
申请日：1996-07-26
申请人： Robert Dawson , Frederick N. Hause , Charles E. May
发明人： Robert Dawson , Frederick N. Hause , Charles E. May
IPC分类号： G01J5/02 , G01J5/00 , G01J5/04 , G01J5/60 , H01L21/26 , G01R31/26 , H01L21/324 , H01L21/477 , H01L21/66
CPC分类号： G01J5/601 , G01J5/041 , G01J5/60
摘要： A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.

4. 发明授权

US06323524B1 Semiconductor device having a vertical active region and method of manufacture thereof 有权
标题翻译：具有垂直有源区的半导体器件及其制造方法
公开(公告)号：US06323524B1
公开(公告)日：2001-11-27
申请号：US09143480
申请日：1998-08-28
申请人： Charles E. May , Robert Dawson
发明人： Charles E. May , Robert Dawson
IPC分类号： H01L2976
CPC分类号： H01L29/41775 , H01L29/41783 , H01L29/66537 , H01L29/66568 , H01L29/66575 , H01L29/6659 , H01L29/66613 , H01L29/66621 , H01L29/66628 , H01L29/78
摘要： A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench. A plurality of doped polysilicon pillars are formed within the trench. The doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.
摘要翻译：提供了一种半导体器件及其制造方法。根据一个实施例，通过在衬底内形成沟槽来形成半导体器件。在沟槽内形成氧化物层，去除氧化物层的部分以暴露沟槽内的衬底的一个或多个部分。多个掺杂的多晶硅柱形成在沟槽内。掺杂的多晶硅柱包括形成在衬底的一个或多个暴露部分上的一个或多个有源区域柱。

5. 发明授权

US06184986B2 Depositing a material of controlled, variable thickness across a surface for planarization of that surface 有权
标题翻译：在表面上沉积受控的，可变厚度的材料，以使该表面平坦化
公开(公告)号：US06184986B2
公开(公告)日：2001-02-06
申请号：US09441222
申请日：1999-11-15
申请人： Robert Dawson , Charles E. May
发明人： Robert Dawson , Charles E. May
IPC分类号： G01B1106
CPC分类号： H01L22/20 , H01L21/31051 , H01L21/32115
摘要： A method is provided for obtaining a topography with a substantially planar upper surface. The profile of the upper surface of the semiconductor topography is first detected by a profile detection tool, such as a stylus profilometer. The profile detection tool creates a database to quantify the elevational variations across the upper surface of the semiconductor topography. The database is then provided to a control system of a deposition tool. The control system controls the deposition of a profile layer upon the upper surface of the semiconductor topography such that a thickness of the profile layer is a function of the elevation of the surface. In one embodiment, the control system controls a potential gradient across the semiconductor topography so as to cause more reactant species to be directed toward the more recessed regions of the topography. In another embodiment, the control system controls the opening and closing of valves disposed within a shower head above the semiconductor topography. More reactant species are allowed to pass from those valves positioned directly above the more recessed regions of the topography. The resulting upper surface of the semiconductor topography is thus planar.
摘要翻译：提供了一种用于获得具有基本平坦的上表面的形貌的方法。首先通过轮廓检测工具（例如触针表面光度计）来检测半导体形貌的上表面的轮廓。轮廓检测工具创建一个数据库，以量化横跨半导体形貌的上表面的高程变化。然后将数据库提供给沉积工具的控制系统。控制系统控制在半导体拓扑的上表面上的轮廓层的沉积，使得轮廓层的厚度是表面的仰角的函数。在一个实施例中，控制系统控制横跨半导体形貌的电位梯度，以便使更多的反应物物质被引导到地形的更凹陷的区域。在另一个实施例中，控制系统控制在半导体形貌之上设置在喷淋头内的阀的打开和关闭。允许更多的反应物物质从位于地形的更凹陷区域正上方的那些阀门通过。因此，所得到的半导体形貌的上表面是平面的。

6. 发明授权

US5981357A Semiconductor trench isolation with improved planarization methodology 失效
标题翻译：具有改进的平面化方法的半导体沟槽隔离
公开(公告)号：US5981357A
公开(公告)日：1999-11-09
申请号：US877000
申请日：1997-06-16
申请人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
发明人： Fred N. Hause , Robert Dawson , Charles E. May , Mark I. Gardner , Kuang-Yeh Chang
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/31053 , Y10S148/05
摘要： An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is performed by repeating the steps of filling isolation trenches, patterning large area isolation trenches, and refilling isolation trenches to present an upper surface having indents which can be readily removed by a chemical-mechanical polish. The silicon mesa upper surface is enhanced by utilizing a unique set of layers stacked upon the silicon substrate, and thereafter patterning the substrate to form raised silicon surfaces, or mesas, having the stacked layers thereon. The patterned, stacked layers include a unique combination of dissimilar compositions which, when removed, leave a silicon mesa upper surface which is recessed below the adjacent, filled trenches. The patterned stacked layers incorporate a polysilicon and/or oxide buffer which prevents deleterious migration of nitrogen from the overlying nitride layer to the underlying silicon mesa upper surface.
摘要翻译：提供隔离技术用于改善填充隔离区相对于相邻硅台面的整体平面度。隔离过程产生具有增强的机械和电性能的硅台面。通过重复填充隔离沟槽，图案化大面积隔离沟槽和重新填充隔离沟槽以呈现具有可以通过化学机械抛光容易去除的凹痕的上表面的步骤来执行平面度。通过利用堆叠在硅衬底上的独特的一组层来增强硅台面上表面，然后对衬底进行图案化以形成其上具有堆叠层的凸起的硅表面或台面。图案化的堆叠层包括不同组合物的独特组合，当被去除时，其离开相邻填充沟槽下方的硅台面上表面。图案化的堆叠层包含多晶硅和/或氧化物缓冲液，其可防止氮从上覆的氮化物层到底层的硅台面上表面的有害迁移。

7. 发明授权

US6044203A Rapid thermal anneal system and method including improved temperature sensing and monitoring 失效
标题翻译：快速热退火系统和方法包括改进的温度检测和监测
公开(公告)号：US6044203A
公开(公告)日：2000-03-28
申请号：US907295
申请日：1997-08-06
申请人： Robert Dawson , Frederick N. Hause , Charles E. May
发明人： Robert Dawson , Frederick N. Hause , Charles E. May
IPC分类号： G01J5/02 , G01J5/00 , G01J5/04 , G01J5/60 , H01L21/26 , H01L21/31 , G01J5/06
CPC分类号： G01J5/601 , G01J5/041 , G01J5/60
摘要： A broadband pyrometer is used for sensing temperature of a semiconductor wafer in an RTA system in association with a monochromator to cancel the backside characteristics of the semiconductor wafer. A rapid thermal anneal (RTA) system includes a rapid thermal anneal (RTA) chamber, a heating lamp arranged in the vicinity of the RTA chamber for heating interior to the RTA chamber, a broadband pyrometer disposed in the vicinity of the RTA chamber and directed to measure interior to the RTA chamber, and a grating monochromator connected to the broadband pyrometer.
摘要翻译：使用宽带高温计来检测与单色仪相关联的RTA系统中的半导体晶片的温度，以消除半导体晶片的背面特性。快速热退火（RTA）系统包括快速热退火（RTA）室，布置在RTA室附近的加热灯，用于加热到RTA室内部，宽带高温计设置在RTA室附近并被引导测量RTA室的内部，以及连接到宽带高温计的光栅单色仪。

8. 发明授权

US6033921A Method for depositing a material of controlled, variable thickness across a surface for planarization of that surface 失效
标题翻译：用于在表面上沉积受控的，可变厚度的材料以使该表面平坦化的方法
公开(公告)号：US6033921A
公开(公告)日：2000-03-07
申请号：US56024
申请日：1998-04-06
申请人： Robert Dawson , Charles E. May
发明人： Robert Dawson , Charles E. May
IPC分类号： G01Q60/46 , G01Q80/00 , G01Q90/00 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/321 , H01L21/66 , H01L21/00
CPC分类号： H01L22/20 , H01L21/31051 , H01L21/32115
摘要： A method is provided for obtaining a topography with a substantially planar upper surface. The profile of the upper surface of the semiconductor topography is first detected by a profile detection tool, such as a stylus profilometer. The profile detection tool creates a database to quantify the elevational variations across the upper surface of the semiconductor topography. The database is then provided to a control system of a deposition tool. The control system controls the deposition of a profile layer upon the upper surface of the semiconductor topography such that a thickness of the profile layer is a function of the elevation of the surface. In one embodiment, the control system controls a potential gradient across the semiconductor topography so as to cause more reactant species to be directed toward the more recessed regions of the topography. In another embodiment, the control system controls the opening and closing of valves disposed within a shower head above the semiconductor topography. More reactant species are allowed to pass from those valves positioned directly above the more recessed regions of the topography. The resulting upper surface of the semiconductor topography is thus planar.
摘要翻译：提供了一种用于获得具有基本平坦的上表面的形貌的方法。首先通过轮廓检测工具（例如触针表面光度计）来检测半导体形貌的上表面的轮廓。轮廓检测工具创建一个数据库，以量化横跨半导体形貌的上表面的高程变化。然后将数据库提供给沉积工具的控制系统。控制系统控制在半导体拓扑的上表面上的轮廓层的沉积，使得轮廓层的厚度是表面的仰角的函数。在一个实施例中，控制系统控制横跨半导体形貌的电位梯度，以便使更多的反应物物质被引导到地形的更凹陷的区域。在另一个实施例中，控制系统控制在半导体形貌之上设置在喷淋头内的阀的打开和关闭。允许更多的反应物物质从位于地形的更凹陷区域正上方的那些阀门通过。因此，所得到的半导体形貌的上表面是平面的。

9. 发明授权

US5949126A Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench 失效
标题翻译：在隔离沟槽的暴露表面上采用保护性侧壁间隔物的沟槽隔离结构
公开(公告)号：US5949126A
公开(公告)日：1999-09-07
申请号：US992735
申请日：1997-12-17
申请人： Robert Dawson , Fred N. Hause , Charles E. May
发明人： Robert Dawson , Fred N. Hause , Charles E. May
IPC分类号： H01L21/762 , H01L29/00 , H01L29/76
CPC分类号： H01L21/76224
摘要： A shallow trench isolation structure and method for making the same are presented. In an embodiment, a trench dielectric is formed within a shallow trench that is disposed in a semiconductor substrate comprising single-crystalline silicon. Dielectric spacers are formed upon the opposed sidewall surfaces of a gate conductor arranged upon the semiconductor substrate a spaced distance from the trench dielectric. Formation of these dielectric spacers involves depositing a dielectric material across the semiconductor topography and anisotropically etching the dielectric material from horizontal surfaces more quickly than from the vertical sidewall surfaces of the gate conductor. Etch duration is terminated after a pre-defined lateral thickness of the dielectric material is achieved upon the sidewall surfaces of the gate conductor. The upper surface of the trench dielectric is also attacked by etchants during the formation of the dielectric spacers. The resulting upper surface of the trench dielectric is recessed below the upper surface of the semiconductor substrate. Protective spacers are subsequently formed upon exposed portions of the trench sidewalls between the upper surface of the substrate and the upper surface of the trench dielectric. These protective spacers inhibit silicide formation upon the trench sidewalls during subsequent formation of silicide upon source/drain junctions of the substrate directly adjacent the trench sidewalls.
摘要翻译：提出了一种浅沟槽隔离结构及其制作方法。在一个实施例中，在布置在包括单晶硅的半导体衬底中的浅沟槽内形成沟槽电介质。电介质间隔物形成在布置在半导体衬底上的栅极导体的与沟槽电介质间隔开的相对侧壁表面上。这些电介质间隔物的形成涉及在半导体形貌上沉积电介质材料，并且比从栅极导体的垂直侧壁表面更快地从水平表面各向异性地蚀刻电介质材料。在栅极导体的侧壁表面上实现介电材料的预定横向厚度之后终止蚀刻持续时间。沟槽电介质的上表面在形成电介质间隔物期间也被蚀刻剂侵蚀。所形成的沟槽电介质的上表面在半导体衬底的上表面下方凹进。随后在衬底的上表面和沟槽电介质的上表面之间的沟槽侧壁的暴露部分上形成保护间隔物。这些保护间隔物在随后在与沟槽侧壁直接相邻的衬底的源极/漏极结之后形成硅化物期间阻止在沟槽侧壁上形成硅化物。

10. 发明授权

US5759871A Structure for testing junction leakage of salicided devices fabricated using shallow trench and refill techniques 失效
公开(公告)号：US5759871A
公开(公告)日：1998-06-02
申请号：US687858
申请日：1996-07-26
申请人： Frederick N. Hause , Charles E. May , Robert Dawson
发明人： Frederick N. Hause , Charles E. May , Robert Dawson
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002
摘要： A resistor protect mask is used on a shallow trench isolation device junction to cover a device area except for a strip on the perimeter of the device area. The silicide layer formed on the central surface portion of the device and the strip area on the perimeter of the device upon which silicide formation is prevented forms a test structure for evaluation of junction formation that is immune from the effects of silicide formation on a device trench sidewall. Electrical tests and leakage measurements upon the test structure are compared directly to similar silicide shallow trench isolated devices which do not incorporate the resistor protect mask and shallow trench isolated devices without silicide to determine whether salicide processing is a cause of junction effects including junction leakage and short-circuiting.

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