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71. 发明申请

US20070159874A1 Semiconductor memory device 有权
公开(公告)号：US20070159874A1
公开(公告)日：2007-07-12
申请号：US11717629
申请日：2007-03-14
申请人： Masanao Yamaoka , Kenichi Osada , Kazumasa Yanagisawa
发明人： Masanao Yamaoka , Kenichi Osada , Kazumasa Yanagisawa
IPC分类号： G11C11/00
CPC分类号： G11C11/417 , G11C5/14 , G11C5/148
摘要： When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.

72. 发明授权

US07230477B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07230477B2
公开(公告)日：2007-06-12
申请号：US11296442
申请日：2005-12-08
申请人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yohihiko Yasu , Nobuhiro Oodaira
发明人： Hiroyuki Mizuno , Yusuke Kanno , Kazumasa Yanagisawa , Yohihiko Yasu , Nobuhiro Oodaira
IPC分类号： H01L2/00
CPC分类号： H03K19/0016 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L27/0928 , H01L27/11898 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
摘要翻译：具有第一电路块BLK1，第二电路块DRV1和用于将第一电路块连接到第二电路块的转换电路MIO 1的半导体集成电路器件。第一电路块包括用于施加电源电压的第一模式和用于关断电源电压的第二模式。转换电路具有将第二电路块的输入节点的电位维持在操作电位的功能，从而当第一电路块处于第二模式时抑制穿透电流流动。转换电路（MIO 1〜MIO 4）通常用于连接电路块。

73. 发明授权

US07222272B2 Semiconductor integrated circuit and testing method thereof 失效
标题翻译：半导体集成电路及其测试方法
公开(公告)号：US07222272B2
公开(公告)日：2007-05-22
申请号：US10430319
申请日：2003-05-07
申请人： Yoshio Takazawa , Toshio Yamada , Kazumasa Yanagisawa , Takashi Hayasaka
发明人： Yoshio Takazawa , Toshio Yamada , Kazumasa Yanagisawa , Takashi Hayasaka
IPC分类号： G11C29/26 , G11C29/40
CPC分类号： G11C29/26 , G11C2029/1806 , G11C2029/2602 , G11C2029/3202
摘要： There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.
摘要翻译：提供了多个桥接电路，其将来自连接到不同访问数据宽度的多个存储器的公共测试总线的测试数据信息和地址解码逻辑转换为每个存储器的固有访问数据宽度，并且还将测试地址信息从公共测试总线到每个存储器的固有位格式，将结果提供给相应的存储器。测试地址信息从公共测试总线并行提供给多个存储器以实现并行测试。因此，测试数据信息可以并行地提供给不同数据宽度的多个存储器，并且用于测试地址信息的各个存储器中的地址扫描方向可以根据固有位格式被均匀化到特定方向。因此，可以提高通过用于多个片上存储器的匹配模式的存储器测试效率。

74. 发明申请

US20050232053A1 Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件
公开(公告)号：US20050232053A1
公开(公告)日：2005-10-20
申请号：US11109660
申请日：2005-04-20
申请人： Yuri Azuma , Yoshihiko Yasu , Yasuto Igarashi , Takashi Kuraishi , Kazumasa Yanagisawa
发明人： Yuri Azuma , Yoshihiko Yasu , Yasuto Igarashi , Takashi Kuraishi , Kazumasa Yanagisawa
IPC分类号： H01L21/822 , G11C5/00 , G11C5/14 , H01L27/04 , H03K19/00 , H03K19/0175
CPC分类号： G11C5/147
摘要： A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has a first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed, wherein the second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with the control signal which was responded to when the second power supply state was instructed by the third circuit block to the first circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block.
摘要翻译：提供一种在实现多功能化和省电的同时提高设计效率的半导体集成电路装置。半导体集成电路器件具有第一至第三电路块，并且被置于第一电源状态，其中根据来自第三电路块的指令或第二电源确保第一电路块中的内部电路的操作其中第二电路块具有接收从第一电路块提供的信号的输入单元，并且第二电路块的输入单元具有根据本发明的输入电路，其中内部电路的操作不被保证，当第三电路块向第一电路块指示第二电源状态时响应的控制信号使得将特定信号电平维持为与第二电路块的工作电压无关，而与信号无关由第一电路块提供。

75. 发明授权

US06949782B2 Semiconductor memories 失效
标题翻译：半导体存储器
公开(公告)号：US06949782B2
公开(公告)日：2005-09-27
申请号：US10790183
申请日：2004-03-02
申请人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
发明人： Bryan Atwood , Kazuo Yano , Tomoyuki Ishii , Taro Osabe , Kazumasa Yanagisawa , Takeshi Sakata
IPC分类号： G11C11/00 , G11C11/401 , G11C11/405 , G11C11/406 , G11C11/4076 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/12
CPC分类号： H01L27/105 , G11C11/405 , G11C11/406 , G11C11/4076 , G11C2207/2281 , G11C2207/229 , H01L27/0207 , H01L27/108 , H01L27/1203
摘要： A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.
摘要翻译：本发明提供了高集成度的动态随机存取存储器。此外，提供了一种写入方法，使得减少了二晶体管和三晶体管增益单元存储器的单元尺寸。一种结合了作为写入元件的薄沟道晶体管的动态存储器，使得在本发明的存储器件中实现长的数据存储保持。通过本发明也实现了具有低操作功率和高密度的动态存储单元。

76. 发明申请

US20050099876A1 Semiconductor integrated circuit and data processing system 失效
标题翻译：半导体集成电路和数据处理系统
公开(公告)号：US20050099876A1
公开(公告)日：2005-05-12
申请号：US11010324
申请日：2004-12-14
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F12/08 , G11C7/06 , G11C7/10 , G11C11/401 , G11C11/4091 , G11C11/4093 , G11C7/00 , G11C8/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
摘要翻译：为了提高第一次访问的速度（从先前访问的字线读取访问）到多存储体存储器，使用多存储体存储器宏结构。数据保存在每个存储体的读出放大器中。当对保持的数据进行访问时，输出由读出放大器锁存的数据，从而提高对存储器宏结构的首次访问的速度。即，使每个存储体用作读出放大器高速缓存。为了更好地提高这种感测放大器高速缓存的命中率，访问控制器在访问存储器宏结构之后自我预取下一个地址（已经添加了预定偏移量的地址），以便自我预取中的数据地址由另一个存储体中的读出放大器预读。

77. 发明授权

US06847578B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US06847578B2
公开(公告)日：2005-01-25
申请号：US10729934
申请日：2003-12-09
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F12/08 , G11C7/06 , G11C7/10 , G11C11/401 , G11C11/4091 , G11C11/4093 , G11C7/00
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

78. 发明授权

US06708249B2 Semiconductor integrated circuit and data processing system 失效
公开(公告)号：US06708249B2
公开(公告)日：2004-03-16
申请号：US10101063
申请日：2002-03-20
申请人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
发明人： Kazushige Ayukawa , Seiji Miura , Jun Satoh , Takao Watanabe , Kazumasa Yanagisawa , Yusuke Kanno , Hiroyuki Mizuno
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F12/0215 , G06F12/0893 , G06F13/161 , G06F2212/3042 , G11C7/065 , G11C11/4091 , G11C11/4093 , G11C2207/104 , G11C2207/2245
摘要： To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.

79. 发明授权

US06643182B2 Semiconductor device 有权
公开(公告)号：US06643182B2
公开(公告)日：2003-11-04
申请号：US10245328
申请日：2002-09-18
申请人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
发明人： Kazumasa Yanagisawa , Toshio Sasaki , Satoru Nakanishi , Yoshihiko Yasu
IPC分类号： G11C700
CPC分类号： G11C11/4091 , G11C5/025 , G11C7/065
摘要： A dynamic RAM includes sense amplifiers each formed of a latch circuit consisting of MOSFETs of a first and second conductivity types with the application of a first and second voltages to the sources thereof, respectively, and having a pair of input/output nodes corresponding to a first bit line pair which is connected with a number of dynamic memory cells, and further includes pairs of switching MOSFETs of the first conductivity type which connect selectively an input/output node pair of the latch circuits to a pair of second bit lines provided commonly to a plurality of the first bit line pair in response to the reception of the select signal. The switching MOSFETs have their threshold voltage set smaller in terms of absolute value than the threshold voltage of the MOSFETs of the first conductivity type of the latch circuits, and the select signal has its level of turning off the switching MOSFETs set greater in terms of absolute value than the first voltage with respect to the second voltage.

80. 发明授权

US06611458B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US06611458B2
公开(公告)日：2003-08-26
申请号：US09780393
申请日：2001-02-12
申请人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
发明人： Koichiro Ishibashi , Shoji Shukuri , Kazumasa Yanagisawa , Junichi Nishimoto , Masanao Yamaoka , Masakazu Aoki
IPC分类号： G11C1606
CPC分类号： G11C16/0441 , B82Y10/00 , C04B28/02 , C04B2103/0097 , C04B2111/00017 , C04B2111/00456 , C04B2111/00517 , C04B2111/2092 , G11C16/04 , G11C29/12 , G11C29/789 , G11C29/848 , G11C2216/10 , H01L22/22 , H01L23/53228 , H01L23/544 , H01L24/48 , H01L24/49 , H01L27/0211 , H01L27/105 , H01L27/10897 , H01L2223/5444 , H01L2223/54473 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48472 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/10162 , H01L2924/12042 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , C04B14/04 , C04B14/06 , C04B14/14 , C04B14/16 , C04B20/008 , C04B24/00 , H01L2924/00012 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2224/45099
摘要： To reduce cost of defect redundancy and trimming in a semiconductor integrated circuit having multiple layer wirings and copper wirings, address for salvaging defect of a memory cell array in a semiconductor is stored by using a nonvolatile memory element constituting a floating electrode by a first layer of polysilicon, or the nonvolatile memory element is programmed in testing the semiconductor integrated circuit, thereby, a special process is not needed in forming the nonvolatile memory element, that is, the nonvolatile memory element can be formed in a process of forming CMOS device and apparatus of laser beam for programming is not needed since the programming is carried out in testing, time necessary for programming can be shortened and therefore, testing cost can be reduced.
摘要翻译：为了降低具有多层布线和铜布线的半导体集成电路中的缺陷冗余和修整的成本，通过使用构成浮置电极的非易失性存储元件，通过第一层多晶硅或非易失性存储元件在对半导体集成电路进行测试时被编程，从而在形成非易失性存储元件时不需要特殊工艺，也就是说，可以在形成CMOS器件和器件的过程中形成非易失性存储元件用于编程的激光束不需要，因为在测试中进行编程，可以缩短编程所需的时间，因此可以降低测试成本。

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