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    • 78. 发明申请
    • THIN FILM TRANSISTORS HAVING MULTIPLE DOPED SILICON LAYERS
    • 具有多层掺杂硅层的薄膜晶体管
    • US20110269274A1
    • 2011-11-03
    • US12913846
    • 2010-10-28
    • Gaku FurutaSoo Young ChoiOmori Kenji
    • Gaku FurutaSoo Young ChoiOmori Kenji
    • H01L21/336
    • H01L29/66765G02F1/1362H01L29/78618
    • Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
    • 本发明的实施例一般涉及TFT及其制造方法。 本文公开的TFT是其中有源沟道包括非晶硅的硅基TFT。 在非晶硅上,沉积了多层掺杂硅,其中掺杂硅层的电阻率在与非晶硅层的界面处比与源极和漏极的界面相比更高。 或者,在非晶硅上沉积单个掺杂的硅层,其中单个掺杂层的性质在整个厚度上变化。 在与源极和漏极的界面处具有较低的电阻率是更好的,但较低的电阻率通常意味着较少的衬底生产量。 通过利用多层或分层,可以实现低电阻率。 本文公开的实施例包括低电阻率而不牺牲基板生产量。
    • 79. 发明授权
    • Differential etch rate control of layers deposited by chemical vapor deposition
    • 通过化学气相沉积沉积的层的差分蚀刻速率控制
    • US07988875B2
    • 2011-08-02
    • US12027964
    • 2008-02-07
    • Soo Young ChoiGaku Furuta
    • Soo Young ChoiGaku Furuta
    • C23F3/00
    • H01L21/31116C03C17/34C03C2218/33C23C16/308C23C16/345C23C16/401H01L21/31111
    • A method and apparatus is provided for controlling the etch profile of a multilayer layer stack by depositing a first and second material layer with differential etch rates in the same or different processing chamber. In one embodiment of the invention, a process for etching substrate material is provided including depositing a first silicon-containing material layer having a first etch rate on the substrate surface from a nitrogen-containing precursor at a first flow rate and a silicon-containing precursor, depositing a second silicon-containing material layer having a second etch rate different than the first etch rate on the first silicon-containing material layer from the nitrogen-containing precursor at a second flow rate different than the first flow rate and the silicon-containing precursor, etching the first silicon-containing material layer and the second silicon-containing material layer, and forming a taper etch profile in the first silicon-containing material layer and the second silicon-containing material layer.
    • 提供了一种方法和装置,用于通过在相同或不同的处理室中沉积差分蚀刻速率的第一和第二材料层来控制多层堆叠的蚀刻轮廓。 在本发明的一个实施例中,提供了一种用于蚀刻衬底材料的方法,包括:以第一流速从含氮前体沉积具有第一蚀刻速率的第一含硅材料层,并在第一流速下沉积含硅前体 在第一含硅材料层上以不同于第一流速的第二流量从含氮前体沉积具有与第一蚀刻速率不同的第二蚀刻速率的第二含硅材料层, 蚀刻第一含硅材料层和第二含硅材料层,并在第一含硅材料层和第二含硅材料层中形成锥形蚀刻轮廓。