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1. 发明申请

US20120040536A1 A-SI SEASONING EFFECT TO IMPROVE SIN RUN-TO-RUN UNIFORMITY 有权
标题翻译： A-SI季节效应提高了单机运行的均匀性
公开(公告)号：US20120040536A1
公开(公告)日：2012-02-16
申请号：US13207315
申请日：2011-08-10
申请人： Gaku Furuta , Soo Young Choi , Beom Soo Park , Young-jin Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Beom Soo Park , Young-jin Choi , Omori Kenji
IPC分类号： H01L21/318
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/4404 , H01L21/02274 , H01L21/02299
摘要： Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.
摘要翻译：本发明的实施方案提供了在设置在处理室中的大尺寸基板上沉积含氮材料的方法。在一个实施方案中，一种方法包括处理处理室内的一批衬底，以将一批含有底物的含氮材料从该批衬底上沉积，并在处理该批衬底期间以预定间隔进行调味过程以沉积导电在处理室中设置的腔室部件的表面上的调味层。腔室部件可以包括由裸铝制成而不阳极氧化的气体分配板。在一个示例中，导电调味层可以包括非晶硅，掺杂非晶硅，掺杂硅，掺杂多晶硅，掺杂碳化硅等。

2. 发明授权

US08999847B2 a-Si seasoning effect to improve SiN run-to-run uniformity 有权
标题翻译： a-Si调味效果提高了SiN运行均匀性
公开(公告)号：US08999847B2
公开(公告)日：2015-04-07
申请号：US13207315
申请日：2011-08-10
申请人： Gaku Furuta , Soo Young Choi , Beom Soo Park , Young-jin Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Beom Soo Park , Young-jin Choi , Omori Kenji
IPC分类号： H01L21/311 , H01L21/02 , C23C16/34 , C23C16/44
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/4404 , H01L21/02274 , H01L21/02299
摘要： Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.
摘要翻译：本发明的实施方案提供了在设置在处理室中的大尺寸基板上沉积含氮材料的方法。在一个实施方案中，一种方法包括处理处理室内的一批衬底，以将一批含有底物的含氮材料从该批衬底上沉积，并在处理该批衬底期间以预定间隔进行调味过程以沉积导电在处理室中设置的腔室部件的表面上的调味层。腔室部件可以包括由裸铝制成而不阳极氧化的气体分配板。在一个示例中，导电调味层可以包括非晶硅，掺杂非晶硅，掺杂硅，掺杂多晶硅，掺杂碳化硅等。

3. 发明授权

US08299466B2 Thin film transistors having multiple doped silicon layers 有权
标题翻译：具有多个掺杂硅层的薄膜晶体管
公开(公告)号：US08299466B2
公开(公告)日：2012-10-30
申请号：US12913846
申请日：2010-10-28
申请人： Gaku Furuta , Soo Young Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Omori Kenji
IPC分类号： H01L31/00
CPC分类号： H01L29/66765 , G02F1/1362 , H01L29/78618
摘要： Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
摘要翻译：本发明的实施例一般涉及TFT及其制造方法。本文公开的TFT是其中有源沟道包括非晶硅的硅基TFT。在非晶硅上，沉积了多层掺杂的硅，其中掺杂硅层的电阻率在与非晶硅层的界面处比与源极和漏极的界面相比更高。或者，在非晶硅上沉积单个掺杂的硅层，其中单个掺杂层的性质在整个厚度上变化。在与源极和漏极的界面处具有较低的电阻率是更好的，但较低的电阻率通常意味着较少的衬底生产量。通过利用多层或分层，可以实现低电阻率。本文公开的实施例包括低电阻率而不牺牲基板生产量。

4. 发明申请

US20110269274A1 THIN FILM TRANSISTORS HAVING MULTIPLE DOPED SILICON LAYERS 有权
标题翻译：具有多层掺杂硅层的薄膜晶体管
公开(公告)号：US20110269274A1
公开(公告)日：2011-11-03
申请号：US12913846
申请日：2010-10-28
申请人： Gaku Furuta , Soo Young Choi , Omori Kenji
发明人： Gaku Furuta , Soo Young Choi , Omori Kenji
IPC分类号： H01L21/336
CPC分类号： H01L29/66765 , G02F1/1362 , H01L29/78618
摘要： Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput.
摘要翻译：本发明的实施例一般涉及TFT及其制造方法。本文公开的TFT是其中有源沟道包括非晶硅的硅基TFT。在非晶硅上，沉积了多层掺杂硅，其中掺杂硅层的电阻率在与非晶硅层的界面处比与源极和漏极的界面相比更高。或者，在非晶硅上沉积单个掺杂的硅层，其中单个掺杂层的性质在整个厚度上变化。在与源极和漏极的界面处具有较低的电阻率是更好的，但较低的电阻率通常意味着较少的衬底生产量。通过利用多层或分层，可以实现低电阻率。本文公开的实施例包括低电阻率而不牺牲基板生产量。

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