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    • 72. 发明授权
    • Low defect metrology approach on clean track using integrated metrology
    • 使用综合计量的清洁轨道的低缺陷计量方法
    • US06724476B1
    • 2004-04-20
    • US10261756
    • 2002-10-01
    • Khoi A. PhanBhanwar SinghBharath Rangarajan
    • Khoi A. PhanBhanwar SinghBharath Rangarajan
    • G01N2100
    • G01N21/9501
    • One aspect of the present invention relates to a system and method of monitoring for defects on a wafer before and after forming a photoresist layer on the wafer. The system includes a device fabrication system comprising one or more wafer processing system components for producing a device; a defect metrology system integrated within and on track with the fabrication system operative to inspect the wafer for defects before it proceeds to photoresist processing; and a wafer cleaning system for reducing an amount of defects detected on the front and/or back side of the wafer. If the amount of defects have been sufficiently reduced, the front side of the wafer may be coated with a photoresist. Subsequently, the back side of the wafer may be inspected and cleaned while protecting the front side from damage. Cleaning of the wafer may be performed with a thermal shock treatment, for example.
    • 本发明的一个方面涉及在晶片上形成光致抗蚀剂层之前和之后对晶片上的缺陷进行监测的系统和方法。 该系统包括装置制造系统,其包括用于产生装置的一个或多个晶片处理系统部件; 在制造系统内部和轨道上集成的缺陷计量系统,其操作用于在进行光致抗蚀剂处理之前检查晶片的缺陷; 以及用于减少在晶片的前侧和/或后侧检测到的缺陷量的晶片清洁系统。 如果缺陷的量已经被充分降低,则晶片的前侧可以涂覆有光致抗蚀剂。 随后,可以在保护前侧免受损伤的同时检查和清洁晶片的背面。 例如,可以进行热冲击处理来进行晶片的清洁。
    • 73. 发明授权
    • Use of scatterometry/reflectometry to measure thin film delamination during CMP
    • 在CMP期间使用散射/反射测量薄膜分层
    • US06702648B1
    • 2004-03-09
    • US10277559
    • 2002-10-22
    • Steven C. AvanzinoBhanwar SinghBharath RangarajanRamkumar Subramanian
    • Steven C. AvanzinoBhanwar SinghBharath RangarajanRamkumar Subramanian
    • B24B4900
    • B24B37/013B24B49/12
    • One aspect of the present invention relates to a system and method for examining a wafer for delamination in real time while polishing the wafer. The system comprises a polishing system programmed to planarize one or more film layers formed on at least a portion of a semiconductor wafer surface; a real-time metrology system coupled to the polishing system such that the metrology system examines the layers as they are planarized; and one or more delamination sensors, wherein at least a portion of each sensor is integrated into the polishing system in order to provide data to the metrology system and wherein the sensor comprises at least one optical element to detect delamination during polishing. The method involves polishing at least a portion of an uppermost film layer and examining at least a portion of a layer underlying the uppermost film layer for delamination as the uppermost layer is being polished.
    • 本发明的一个方面涉及一种用于在抛光晶片的同时检查晶片以实时分层的系统和方法。 该系统包括被编程为平坦化形成在半导体晶片表面的至少一部分上的一个或多个膜层的抛光系统; 耦合到抛光系统的实时计量系统,使得计量系统在平面化时对层进行检查; 和一个或多个分层传感器,其中每个传感器的至少一部分被集成到抛光系统中,以便向计量系统提供数据,并且其中传感器包括至少一个光学元件以在抛光期间检测分层。 该方法包括抛光最上面的薄膜层的至少一部分,并且在最上层被抛光时检查最上面的薄膜层下面的层的至少一部分用于分层。
    • 75. 发明授权
    • Monitor CMP process using scatterometry
    • 使用散点法监测CMP过程
    • US06594024B1
    • 2003-07-15
    • US09886863
    • 2001-06-21
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBharath RangarajanCarmen Morales
    • Bhanwar SinghRamkumar SubramanianKhoi A. PhanBharath RangarajanCarmen Morales
    • G01B1128
    • B24B37/005B24B49/12G01N21/47G01N21/9501H01L21/30625
    • One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.
    • 本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统,以便确定包括晶片的CMP工艺端点,其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库,以确定晶片的状态。 另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法,其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。
    • 76. 发明授权
    • Measure fluorescence from chemical released during trim etch
    • 测量在修剪蚀刻期间释放的化学物质的荧光
    • US06448097B1
    • 2002-09-10
    • US09911236
    • 2001-07-23
    • Bhanwar SinghBharath RangarajanRamkumar Subramanian
    • Bhanwar SinghBharath RangarajanRamkumar Subramanian
    • H01L3126
    • G01N21/64G01N2021/6417H01L22/26
    • A system and method is provided for determining and controlling development of a semiconductor substrate employing fluorescence spectroscopy. One aspect of the invention relates to a system and method employing fluorescence spectroscopy to facilitate control of a chemical trim etch process during development of a photoresist material layer. The chemical trim etch process comprises applying a trim compound or material to a patterned photoresist. The trim compound or material is diffusable into the sides and top of the patterned resist. The diffused regions of the resist are soluble in a developer, which facilitates creating smaller features in the patterned photoresist. The fluorescence spectroscopy system can be employed to measure isolated and dense gratings or CDs and use the evolution of the CD to determine when to terminate the chemical trim process.
    • 提供了一种使用荧光光谱法确定和控制半导体衬底的开发的系统和方法。 本发明的一个方面涉及使用荧光光谱学来促进在光致抗蚀剂材料层的显影期间控制化学修剪蚀刻工艺的系统和方法。 化学修剪蚀刻工艺包括将修剪化合物或材料施加到图案化的光致抗蚀剂上。 修整组合物或材料可扩散到图案化抗蚀剂的侧面和顶部。 抗蚀剂的扩散区域可溶于显影剂,这有助于在图案化的光致抗蚀剂中产生更小的特征。 荧光光谱系统可用于测量孤立和致密的光栅或CD,并使用CD的演变来确定何时终止化学修饰过程。
    • 77. 发明授权
    • Common nozzle for resist development
    • 普通喷嘴用于抗蚀剂开发
    • US06322009B1
    • 2001-11-27
    • US09429992
    • 1999-10-29
    • Ramkumar SubramanianKhoi A. PhanBharath RangarajanBhanwar Singh
    • Ramkumar SubramanianKhoi A. PhanBharath RangarajanBhanwar Singh
    • B05B900
    • H01L21/6708H01L21/67051
    • A combination nozzle for applying a developer material and a washing solution material at different time intervals to a photoresist material layer disposed on a wafer is provided. The combination nozzle includes a number of developer nozzle tips connected to a developer supply line and a number of washing solution nozzle tips connected to a washing solution supply line. The developer supply line and the washing solution supply line ensure that the developer material and the washing solution material are always substantially isolated from one another. Furthermore, the developer nozzle tips and the washing solution nozzle tips are arranged so that developer material and washing solution material do not come into contact with one another. The volume of the material and the volume flow of the material can be controlled by electronically controlled valves.
    • 提供了用于将显影剂材料和洗涤液材料以不同的时间间隔施加到设置在晶片上的光致抗蚀剂材料层的组合喷嘴。 组合喷嘴包括连接到显影剂供应管线的多个显影剂喷嘴尖端和连接到洗涤溶液供应管线的多个洗涤溶液喷嘴尖端。 显影剂供应管线和洗涤溶液供应管线确保显影剂材料和洗涤液材料总是基本上彼此隔离。 此外,显影剂喷嘴尖端和洗涤溶液喷嘴尖端被布置成使得显影剂材料和洗涤液材料彼此不接触。 材料的体积和材料的体积流量可以通过电子控制阀来控制。
    • 78. 发明授权
    • Reverse lithographic process for semiconductor vias
    • 半导体通孔反向光刻工艺
    • US06221777B1
    • 2001-04-24
    • US09329154
    • 1999-06-09
    • Bhanwar SinghBharath RangarajanUrsula Q. Quinto
    • Bhanwar SinghBharath RangarajanUrsula Q. Quinto
    • H01L2100
    • H01L27/11521H01L21/76802H01L21/76816
    • A reverse lithographic process is provided for more densely packing semiconductors onto a semiconductor wafer. A semiconductor wafer having a dielectric covered semiconductor device has a photoresist deposited which is patterned with vias in closely packed rows and columns. The resist is developed and trimmed to form via photoresist structures. A non-photosensitive polymer is deposited over the via photoresist structures and, when hardened, is subject to planarizing to expose the via photoresist structures. The via photoresist structures are removed and leave a reverse image patterned polymer. The photoresist is removed leaving the reverse image patterned polymer, which is then used to etch the dielectric to form vias to the semiconductor device.
    • 提供反向光刻工艺用于在半导体晶片上更密集地堆叠半导体。 具有电介质覆盖的半导体器件的半导体晶片具有沉积的光致抗蚀剂,其以紧密堆积的行和列形成通孔。 抗蚀剂被显影和修整以通过光致抗蚀剂结构形成。 非光敏聚合物沉积在通孔光致抗蚀剂结构上,并且当硬化时,进行平面化以暴露通孔光致抗蚀剂结构。 去除通孔光致抗蚀剂结构并留下反向图案图案化的聚合物。 除去光致抗蚀剂留下反向图案图案化的聚合物,然后将其用于蚀刻电介质以形成到半导体器件的通孔。
    • 79. 发明授权
    • Focus monitor structure and method for lithography process
    • 光刻工艺的聚焦监视器结构和方法
    • US6063531A
    • 2000-05-16
    • US167417
    • 1998-10-06
    • Bhanwar SinghBharath RangarajanKhoi Anh PhanCarmen L. Morales
    • Bhanwar SinghBharath RangarajanKhoi Anh PhanCarmen L. Morales
    • G03F7/20G03F9/02G03F9/00
    • G03F7/70625G03F7/70641
    • A focus monitor structure is placed on a reticle or mask near the production device structures, such as integrated circuits, to monitor the focal conditions of the lithography process as well as other parameters, such as the critical dimension, and proximity effects. The focus monitor structure includes a series of densely packed parallel lines and an isolated line along with a line that is positioned orthogonally to the densely packed lines forming an "L" shaped structure. The focus monitor structure also includes a plurality of rectangular islands that create post structures when patterned in the resist layer. The lines of the focus monitor structure are approximately the critical dimension and the rectangular islands vary in width between .+-.10% of the critical dimension. By manually or automatically inspecting the focus monitor structure after it is patterned into a layer of resist, including measuring the width of the resist lines and the resist profile angle of the orthogonal line, information relating to the critical dimension as well as the focal conditions of the lithography process can be determined.
    • 将聚焦监视器结构放置在生产设备结构(例如集成电路)附近的掩模版或掩模上,以监视光刻工艺的焦点状况以及其他参数,例如临界尺寸和邻近效应。 聚焦监视器结构包括一系列密集的平行线和一条隔离的线以及一条线,该线与形成“L”形结构的密集线相正交。 聚焦监视器结构还包括当在抗蚀剂层中图案化时产生柱结构的多个矩形岛。 聚焦监视器结构的线条大致是临界尺寸,矩形岛的宽度在临界尺寸的+/- 10%之间变化。 在聚焦监视器结构被图案化成抗蚀剂层之后,通过手动或自动地检查聚焦监视器结构,包括测量抗蚀剂线的宽度和正交线的抗蚀剂轮廓角,与关键尺寸以及焦点监视结构的焦点条件 可以确定光刻工艺。