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71. 发明授权

US6065028A Multifunctional macro 失效
标题翻译：多功能宏
公开(公告)号：US6065028A
公开(公告)日：2000-05-16
申请号：US716818
申请日：1996-09-16
申请人： Sang Hoo Dhong , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F9/302 , G06F9/305 , G06F9/315 , G06F7/38
CPC分类号： G06F9/3001 , G06F9/30029 , G06F9/30032
摘要： Fixed point instructions ADD, ROTATE, COMPARE-TO-ZERO, AND, OR and COUNT-LEADING-ZEROS are each performable in one circuit or macro. Such fixed point instructions may be implemented within an execution unit in a microprocessor, microcontroller, or digital signal processor.
摘要翻译：固定点指令ADD，ROTATE，COMPARE-TO-ZERO，AND，OR和COUNT-LEADING-ZEROS都可以在一个电路或宏中执行。这样的固定点指令可以在微处理器，微控制器或数字信号处理器的执行单元内实现。

72. 发明授权

US6035390A Method and apparatus for generating and logically combining less than (LT), greater than (GT), and equal to (EQ) condition code bits concurrently with the execution of an arithmetic or logical operation 失效
标题翻译：用于与执行算术或逻辑运算同时产生和逻辑组合小于（LT），大于（GT）和等于（EQ））条件码位的方法和装置
公开(公告)号：US6035390A
公开(公告)日：2000-03-07
申请号：US5471
申请日：1998-01-12
申请人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
发明人： Jeffrey L. Burns , Sang Hoo Dhong , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G06F9/38 , G06F7/48 , G06F9/302 , G06F9/305 , G06F9/32 , G06F9/30
CPC分类号： G06F9/3001 , G06F7/48 , G06F9/30094
摘要： A processor includes at least an execution unit that executes an instruction by performing an operation indicated by the instruction utilizing one or more operands and condition code logic that determines less than, greater than, and equal to condition code bits associated with the instruction concurrently with execution of the instruction by the execution unit. In one embodiment, the condition code logic includes a single computation stage that receives as inputs individual bit values of bit positions within first and second operands and logically combines the individual bit values. The single computation stage outputs, for each bit position, propagate, generate, and kill signals that collectively indicate values for the less than, greater than, and equal to condition code bits. One or more merging stages coupled to the computation stage then merge the propagate, generate, and kill signals into output signals that set the condition code bits.
摘要翻译：处理器至少包括一个执行单元，该执行单元通过使用一个或多个操作数和条件代码逻辑执行指令所指示的操作来执行指令，所述操作数和条件代码逻辑确定小于，大于和等于与执行同时执行的指令相关联的条件代码位的执行单元的指令。在一个实施例中，条件码逻辑包括单个计算阶段，其接收第一和第二操作数中的比特位置的各个比特值作为输入，并逻辑地组合各个比特值。对于每个位位置，单个计算级输出传播，产生和去除共同指示小于，大于和等于条件码位的值的信号。耦合到计算阶段的一个或多个合并阶段然后将传播，生成和终止信号合并到设置条件码位的输出信号中。

73. 发明授权

US6014763A At-speed scan testing 失效
标题翻译：高速扫描测试
公开(公告)号：US6014763A
公开(公告)日：2000-01-11
申请号：US7670
申请日：1998-01-15
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Kevin John Nowka , Joel Abraham Silberman
IPC分类号： G01R31/28
CPC分类号： G01R31/318572
摘要： A method of scanning an integrated circuit, by converting a parallel scan input (scan data and scan control) to serial, passing the serial scan input through scan circuitry to create a serial scan output, converting the scan output from serial to parallel, transmitting the scan output in parallel from the integrated circuit to the tester. A tester clock signal is derived by synchronizing the tester to a divided clock signal (1/N) of the integrated circuit. Communications take place at a speed of the tester clock signal, but the scan operates at the full operational speed of the device under test. At-speed scan testing can be achieved for speeds in excess of 1 GHz.
摘要翻译：通过将并行扫描输入（扫描数据和扫描控制）转换为串行扫描来扫描集成电路的方法，将串行扫描输入通过扫描电路传送以创建串行扫描输出，将扫描输出从串行转换为并行转换，从集成电路并行扫描输出到测试仪。通过将测试仪与集成电路的分频时钟信号（1 / N）同步，得到测试仪时钟信号。通信以测试仪时钟信号的速度进行，但扫描以被测设备的全部操作速度运行。对于超过1 GHz的速度，可以实现高速扫描测试。

74. 发明授权

US5964827A High-speed binary adder 失效
标题翻译：高速二进制加法器
公开(公告)号：US5964827A
公开(公告)日：1999-10-12
申请号：US971653
申请日：1997-11-17
申请人： Hung Cai Ngo , Sang Hoo Dhong , Joel Abraham Silberman
发明人： Hung Cai Ngo , Sang Hoo Dhong , Joel Abraham Silberman
IPC分类号： G06F7/50 , G06F7/508 , G06F7/52
CPC分类号： G06F7/508
摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple four-bit group generate circuits and multiple four-bit group propagate circuits. Each of the four-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the four-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
摘要翻译：公开了一种高速进位 - 前瞻二进制加法器。二进制加法器包括多行进位查找电路，半和模块和和/进位模块。第一进位 - 前瞻电路行包括多个四位组生成电路和多个四位组传播电路。四位组生成电路中的每一个产生相应位位置的生成信号。四位组传播电路中的每一个产生用于相应位位置的传播信号。半和模块用于产生半和信号。通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

75. 发明申请

US20090116307A1 LEVEL SHIFTER FOR BOOSTING WORDLINE VOLTAGE AND MEMORY CELL PERFORMANCE 有权
标题翻译：提高字线电压和存储单元性能的级别更换
公开(公告)号：US20090116307A1
公开(公告)日：2009-05-07
申请号：US11935741
申请日：2007-11-06
申请人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
发明人： Scott R. Cottier , Sang Hoo Dhong , Rajiv V. Joshi , Juergen Pille , Osamu Takahashi
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/418
摘要： A circuit and method includes first circuits powered by a first supply voltage and second circuits powered by a second supply voltage. A level shifter is coupled between the first circuits and the second circuits. The level shifter is configured to select a supply voltage output for a circuit including one of the first supply voltage and the second supply voltage in accordance an input signal, where the input signal depends on at least one of an operation to be performed and component performing the operation.
摘要翻译：电路和方法包括由第一电源电压供电的第一电路和由第二电源电压供电的第二电路。电平移位器耦合在第一电路和第二电路之间。电平移位器被配置为根据输入信号选择包括第一电源电压和第二电源电压中的一个的电路的电源电压输出，其中输入信号取决于要执行的操作和组件执行中的至少一个的操作。

76. 发明授权

US07444525B2 Methods and apparatus for reducing leakage current in a disabled SOI circuit 有权
标题翻译：用于减少残留SOI电路中漏电流的方法和装置
公开(公告)号：US07444525B2
公开(公告)日：2008-10-28
申请号：US11137234
申请日：2005-05-25
申请人： Hiroshi Yoshihara , Sang Hoo Dhong , Osamu Takahashi , Takaaki Nakazato
发明人： Hiroshi Yoshihara , Sang Hoo Dhong , Osamu Takahashi , Takaaki Nakazato
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： H03K19/0016
摘要： Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.
摘要翻译：方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

77. 发明授权

US07203608B1 Impedane measurement of chip, package, and board power supply system using pseudo impulse response 有权
标题翻译：使用伪冲击响应的芯片，封装和板电源系统的Impedane测量
公开(公告)号：US07203608B1
公开(公告)日：2007-04-10
申请号：US11424613
申请日：2006-06-16
申请人： Makoto Aikawa , Sang Hoo Dhong , Brian Flachs , Paul Marlan Harvey , Brad William Michael , Yaping Zhou
发明人： Makoto Aikawa , Sang Hoo Dhong , Brian Flachs , Paul Marlan Harvey , Brad William Michael , Yaping Zhou
IPC分类号： G01R27/28
CPC分类号： G01R27/16 , G01R27/205 , G01R31/3008
摘要： A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement. The mechanism of the present invention then calculates the impedance of the chip/package/board power supply system using the voltage measurement and the second current measurement.
摘要翻译：一种用于测量微处理器芯片，电子封装和电路板电源系统的阻抗的方法，其通过产生具有不大于感兴趣的最大频率的反转的时域中的宽度尺寸的伪脉冲电流并获得电压测量在伪脉冲电流的频域中。然后，本发明的机构预测频域中的电流的归一化傅里叶变换，其中归一化傅里叶变换取决于伪脉冲电流的切换电荷，测量伪脉冲电流的开关电荷，获得使用测量的开关电荷在零频率下的第一电流测量，并且使用第一电流测量获得感兴趣频率的第二电流测量。然后，本发明的机构使用电压测量和第二电流测量来计算芯片/封装/板电源系统的阻抗。

78. 发明授权

US07170316B2 Programmable logic array latch 失效
标题翻译：可编程逻辑阵列锁存器
公开(公告)号：US07170316B2
公开(公告)日：2007-01-30
申请号：US10982018
申请日：2004-11-05
申请人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
摘要翻译：公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。第二逻辑阵列耦合到第一逻辑阵列。输出锁存器耦合到第二逻辑阵列。

79. 发明授权

US06927615B2 Low skew, power efficient local clock signal generation system 失效
标题翻译：低偏移，功率有效的本地时钟信号发生系统
公开(公告)号：US06927615B2
公开(公告)日：2005-08-09
申请号：US10455178
申请日：2003-06-05
申请人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
发明人： Sang Hoo Dhong , Joel Abraham Silberman , Osamu Takahashi , James Douglas Warnock , Dieter Wendel
IPC分类号： G06F1/04 , G06F1/10 , H03K3/00
CPC分类号： G06F1/10
摘要： A local clock signal generation system is disclosed including multiple local clock buffers each receiving a global clock signal and producing a version of one or more local clock signals derived from the global clock signal. Each local clock buffer includes an input section and an output section. The input sections are substantially identical such that timing differences between the versions of the one or more local clock signals are reduced. An electronic circuit is described including the local clock signal generation system and a latch (e.g., a master latch of a flip-flop). A local clock buffer produces a gating signal and a local clock signal received by the latch. When the gating signal is a certain logic value, the local clock signal is a steady logic value, and the latch produces an input data signal as an output signal. An integrated circuit including the electronic circuit is disclosed.
摘要翻译：公开了本地时钟信号产生系统，其包括多个本地时钟缓冲器，每个时钟缓冲器接收全局时钟信号并产生从全局时钟信号导出的一个或多个本地时钟信号的版本。每个本地时钟缓冲器包括输入部分和输出部分。输入部分基本相同，使得一个或多个本地时钟信号的版本之间的定时差减小。描述了包括本地时钟信号产生系统和锁存器（例如，触发器的主锁存器）的电子电路。本地时钟缓冲器产生门控信号和由锁存器接收到的本地时钟信号。当门控信号为某一逻辑值时，本地时钟信号为稳定逻辑值，锁存器产生输入数据信号作为输出信号。公开了一种包括电子电路的集成电路。

80. 发明授权

US06885596B2 Apparatus and method of wordline/bitline redundancy control using shift registers in an SRAM 失效
标题翻译：使用SRAM中的移位寄存器进行字线/位线冗余控制的装置和方法
公开(公告)号：US06885596B2
公开(公告)日：2005-04-26
申请号：US10606584
申请日：2003-06-26
申请人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
发明人： Toru Asano , Sang Hoo Dhong , Takaaki Nakazato , Osamu Takahashi
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/806
摘要： A decoder for use in wordline/bitline redundancy control is disclosed. In one aspect, the decoder includes first and second wordlines respectively coupled to redundant first and second wordlines, where the first and second wordlines are configured to be activated based on decoded first and second addresses. In addition, the decoder includes first and second shift registers respectively coupled to the redundant first and second wordlines, where each is configured to respectively activate the redundant first and second wordlines when the first or second wordlines contain a defect. In addition, a method of selecting wordlines for use in wordline/bitline redundancy control and a wordline decoder having redundancy control capabilities are also disclosed.
摘要翻译：公开了一种用于字线/位线冗余控制的解码器。在一个方面，解码器包括分别耦合到冗余第一和第二字线的第一和第二字线，其中第一和第二字线被配置为基于经解码的第一和第二地址被激活。此外，解码器包括分别耦合到冗余第一和第二字线的第一和第二移位寄存器，其中每个被配置为当第一或第二字线包含缺陷时分别激活冗余第一和第二字线。此外，还公开了一种用于字线/位线冗余控制中使用的字线的方法和具有冗余控制能力的字线解码器。

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