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1. 发明授权

US07170316B2 Programmable logic array latch 失效
标题翻译：可编程逻辑阵列锁存器
公开(公告)号：US07170316B2
公开(公告)日：2007-01-30
申请号：US10982018
申请日：2004-11-05
申请人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Brian K. Flachs , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K19/177 , G06F7/38
CPC分类号： H03K19/1772
摘要： A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.
摘要翻译：公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。第二逻辑阵列耦合到第一逻辑阵列。输出锁存器耦合到第二逻辑阵列。

2. 发明授权

US07746140B2 Scannable latch 有权
标题翻译：可扫描闩锁
公开(公告)号：US07746140B2
公开(公告)日：2010-06-29
申请号：US11550997
申请日：2006-10-19
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

3. 发明授权

US07170328B2 Scannable latch 失效
标题翻译：可扫描闩锁
公开(公告)号：US07170328B2
公开(公告)日：2007-01-30
申请号：US10982112
申请日：2004-11-05
申请人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
发明人： Sang Hoo Dhong , Joel A. Silberman , Osamu Takahashi
IPC分类号： H03K3/289 , H03K3/356
CPC分类号： H03K3/356113 , G01R31/318541
摘要： A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.
摘要翻译：公开了可扫描的闩锁。可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

4. 发明授权

US08576000B2 3D chip stack skew reduction with resonant clock and inductive coupling 有权
标题翻译：具有谐振时钟和电感耦合的3D芯片堆栈倾斜减少
公开(公告)号：US08576000B2
公开(公告)日：2013-11-05
申请号：US13217349
申请日：2011-08-25
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.
摘要翻译：提供了一种时钟分配网络，用于在具有两个或更多个层的3D芯片堆栈内同步全局时钟信号。时钟分配网络包括多个时钟分配电路，每个时钟分配电路被布置在两个或更多个层中的相应一个上，用于将全局时钟信号提供给各种芯片位置。多个时钟分配电路中的每一个包括用于为时钟分配网络提供层间层耦合的谐振电路。谐振电路包括至少一个电容器和至少一个电感器。

5. 发明申请

US20100257336A1 Dependency Matrix with Reduced Area and Power Consumption 失效
标题翻译：具有减小面积和功耗的依赖矩阵
公开(公告)号：US20100257336A1
公开(公告)日：2010-10-07
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/44 , G06F15/00 , G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

6. 发明授权

US5881274A Method and apparatus for performing add and rotate as a single instruction within a processor 失效
标题翻译：用于在处理器内作为单个指令执行加法和旋转的方法和装置
公开(公告)号：US5881274A
公开(公告)日：1999-03-09
申请号：US900261
申请日：1997-07-25
申请人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
发明人： Hung C. Ngo , Joel A. Silberman , Sang H. Dhong
IPC分类号： G06F9/302 , G06F9/315 , G06F9/305
CPC分类号： G06F9/3001 , G06F9/30032
摘要： An apparatus for performing ADD and ROTATE as a single instruction within a processor is disclosed. In accordance with a preferred embodiment of the present invention, the apparatus comprises an adder and a rotator. The adder is utilized for adding a first number to a second number in a multiple stages to yield a carry-out and a sum output. During each of these stages, the adder produces a group generate value and a group propagate value. The rotator is utilized for rotating the group propagate value and the group generate value at each of the stages before the yielding of the carry-out and the sum output. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.
摘要翻译：公开了一种用于在处理器内执行ADD和ROTATE作为单个指令的装置。根据本发明的优选实施例，该装置包括加法器和旋转器。加法器用于将多个第一数字加到多个第二数目中以产生一个进位输出和一个和输出。在每个阶段中，加法器产生组生成值和组传播值。旋转器用于旋转组传播值，并且在进位输出和总和输出的屈服之前的组中的每个级产生组生成值。因此，ADD和ROTATE指令都可以在单个处理器周期内完成。

7. 发明授权

US08519735B2 Programming the behavior of individual chips or strata in a 3D stack of integrated circuits 有权
公开(公告)号：US08519735B2
公开(公告)日：2013-08-27
申请号：US13217734
申请日：2011-08-25
申请人： Liang-Teck Pang , Joel A. Silberman , Matthew R. Wordeman
发明人： Liang-Teck Pang , Joel A. Silberman , Matthew R. Wordeman
IPC分类号： H03K19/00
CPC分类号： G01R31/318558 , G01R31/318513 , G01R31/318572 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

8. 发明授权

US08466739B2 3D chip stack skew reduction with resonant clock and inductive coupling 有权
公开(公告)号：US08466739B2
公开(公告)日：2013-06-18
申请号：US13607089
申请日：2012-09-07
申请人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
发明人： Jae-Joon Kim , Yu-Shiang Lin , Liang-Teck Pang , Joel A. Silberman
IPC分类号： H01L25/00
CPC分类号： H03L7/00 , G06F1/10 , H01L2924/0002 , H01L2924/00
摘要： There is provided a clock distribution network for synchronizing global clock signals within a 3D chip stack having two or more strata. The clock distribution network includes a plurality of clock distribution circuits, each being arranged on a respective one of the two or more strata for providing the global clock signals to various chip locations. Each of the plurality of clock distribution circuits includes a resonant circuit for providing stratum-to-stratum coupling for the clock distribution network. The resonant circuit includes at least one capacitor and at least one inductor.

9. 发明授权

US08127116B2 Dependency matrix with reduced area and power consumption 失效
标题翻译：具有减少面积和功耗的依赖矩阵
公开(公告)号：US08127116B2
公开(公告)日：2012-02-28
申请号：US12417768
申请日：2009-04-03
申请人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
发明人： Saiful Islam , Mary D. Brown , Bjorn P. Christensen , Sam G. Chu , Robert A. Cordes , Maureen A. Delaney , Jafar Nahidi , Joel A. Silberman
IPC分类号： G06F9/30
CPC分类号： G06F9/3838
摘要： A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.
摘要翻译：具有依赖矩阵的处理器包括包括多个第一单元的第一阵列。第二阵列耦合到第一阵列并且包括多个第二单元。第一个写入端口耦合到第一个阵列和第二个阵列，并写入第一个阵列和第二个阵列。第一读端口耦合到第一阵列和第二阵列，并从第一阵列和第二阵列读取。第二个读取端口耦合到第一个数组并从第一个数组读取。第二个写入端口耦合到第二个读取端口，从第二个读取端口读取并写入第二个数据。

10. 发明申请

US20080195850A1 Method and System for Restoring Register Mapper States for an Out-Of-Order Microprocessor 失效
标题翻译：用于为无序微处理器恢复寄存器映射器状态的方法和系统
公开(公告)号：US20080195850A1
公开(公告)日：2008-08-14
申请号：US11674754
申请日：2007-02-14
申请人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
发明人： Christopher M. Abernathy , Mary D. Brown , Dung Q. Nguyen , Joel A. Silberman
IPC分类号： G06F9/38
CPC分类号： G06F9/3863 , G06F9/3802 , G06F9/384 , G06F9/3842 , G06F9/3885
摘要： A method of restoring register mapper states for an out-of-order microprocessor. A processor maps a logical register to a physical register in a map table in response to a first instruction. Instruction sequencing logic records a second speculatively executed instruction as a most recently dispatched instruction in the map table when the second instruction maps the same logical register of the first instruction. The instruction sequencing logic sets an evictor instruction tag (ITAG) of the first instruction in the map table when the second instruction maps a same logical register of the first instruction. The instruction sequencing logic detects mispredicted speculative instructions, determines which instructions in the map table were dispatched prior to the mispredicted speculative instructions, and restores the map table to a state prior to the mispredicted speculative instructions by utilizing the evictor ITAG to restore one or more A bits in the map table data structure.
摘要翻译：一种恢复无序微处理器的寄存器映射器状态的方法。处理器响应于第一指令将逻辑寄存器映射到地图表中的物理寄存器。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑将第二推测执行指令记录为映射表中最近调度的指令。当第二指令映射第一指令的相同逻辑寄存器时，指令排序逻辑设置映射表中的第一指令的撤销指令标签（ITAG）。指令排序逻辑检测误预测的推测指令，确定映射表中的哪些指令在误预测的推测指令之前被分派，并且通过利用驱逐者ITAG恢复一个或多个A，将映射表恢复到误预测的推测指令之前的状态位图中的数据结构。

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