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1. 发明授权

US6153508A Multi-layer circuit having a via matrix interlayer connection and method for fabricating the same 失效
标题翻译：具有通孔矩阵层间连接的多层电路及其制造方法
公开(公告)号：US6153508A
公开(公告)日：2000-11-28
申请号：US26090
申请日：1998-02-19
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L23/12 , H05K1/11 , H05K3/40 , H05K3/42 , H05K3/46 , H01L21/4763
CPC分类号： H05K1/115 , H05K3/42 , H05K2201/09781 , H05K2201/0979
摘要： An interlayer connection for electrically connecting first and second conductive elements and reducing interlayer registration requirements is disclosed. The interlayer connection includes a first layer including a first electrically conductive element, a second layer including a second electrically conductive element, and a third layer disposed between the first layer and the second layer. The third layer includes an electrically insulative portion having a matrix of immediately adjacent vias therethrough. A selected plurality of immediately adjacent vias within the matrix are disposed between the first and the second electrically conductive elements and contain electrically conductive material forming a conductive path between the first and the second electrically conductive elements.
摘要翻译：公开了一种用于电连接第一和第二导电元件并减少层间配准要求的层间连接。层间连接包括包括第一导电元件的第一层，包括第二导电元件的第二层和设置在第一层和第二层之间的第三层。第三层包括具有通过其直接相邻的通孔的矩阵的电绝缘部分。矩阵内的所选择的多个紧邻的通孔设置在第一和第二导电元件之间，并且包含在第一和第二导电元件之间形成导电路径的导电材料。

2. 发明申请

US20120098116A1 MULTI-CHIP MODULE SYSTEM WITH REMOVABLE SOCKETED MODULES 有权
标题翻译：具有可拆卸模块的多芯片模块系统
公开(公告)号：US20120098116A1
公开(公告)日：2012-04-26
申请号：US12909980
申请日：2010-10-22
申请人： Jon Alfred Casey , John Lee Colbert , Paul Marlan Harvey , Mark Kenneth Hoffmeyer , Charles L. Reynolds
发明人： Jon Alfred Casey , John Lee Colbert , Paul Marlan Harvey , Mark Kenneth Hoffmeyer , Charles L. Reynolds
IPC分类号： H01L23/36 , H01L21/60
CPC分类号： H01L23/49833 , H01L22/14 , H01L23/32 , H01L23/4006 , H01L23/467 , H01L2924/16251 , H01L2924/16747
摘要： A multi-chip module (MCM) includes chip sub-modules that are fabricated as self-contained testable entities. The chip sub-modules plug into respective sockets in a frame of the MCM. Each chip sub-module may be tested before being plugged into the MCM. A chip sub-module may include an IC chip, such as a processor, mounted to an sub-module organic substrate that provides interconnects to the chip. The frame into which each chip sub-module plugs sits on a mini-card organic substrate that interconnects the chip sub-modules together. The MCM may include a downstop between the mini-card organic substrate and a system board to limit or prevent solder creep of solder connections between the mini-card organic substrate and the system board.
摘要翻译：多芯片模块（MCM）包括作为独立可测试实体制造的芯片子模块。芯片子模块插入MCM框架中的相应插槽。在插入MCM之前，可以对每个芯片子模块进行测试。芯片子模块可以包括安装到向模块提供互连的子模块有机衬底的诸如处理器的IC芯片。每个芯片子模块插入的框架位于将芯片子模块互连在一起的微型卡有机基板上。 MCM可以包括微卡有机基板和系统板之间的下停，以限制或防止微卡有机基板和系统板之间的焊料连接的焊料蠕变。

3. 发明授权

US08153516B2 Method of ball grid array package construction with raised solder ball pads 有权
标题翻译：球形阵列封装结构的方法与凸起焊球垫
公开(公告)号：US08153516B2
公开(公告)日：2012-04-10
申请号：US12857832
申请日：2010-08-17
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L21/44 , H01L21/00
CPC分类号： H01L23/49816 , H01L25/0657 , H01L2224/16225 , H01L2225/06513 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K3/3457 , H05K3/4652 , H05K2201/098 , H05K2201/0989 , Y02P70/611 , H01L2224/0401
摘要： The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.
摘要翻译：本发明提供了一种BGA焊球与具有下层电路层的叠层电路组件的外导电层的互连。本发明包括与外部导电层基本上共面的升高的BGA焊球垫，凸起垫具有凸起面和多个垂直导电壁以及具有大于凸起宽度的平均直径的BGA焊球 BGA焊球粘附到凸起面和垂直导电壁的大部分上。

4. 发明申请

US20100308460A1 Method of Ball Grid Array Package Construction with Raised Solder Ball Pads 有权
标题翻译：球形阵列封装结构与引脚焊球的方法
公开(公告)号：US20100308460A1
公开(公告)日：2010-12-09
申请号：US12857832
申请日：2010-08-17
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/49816 , H01L25/0657 , H01L2224/16225 , H01L2225/06513 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K3/3457 , H05K3/4652 , H05K2201/098 , H05K2201/0989 , Y02P70/611 , H01L2224/0401
摘要： The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.
摘要翻译：本发明提供了一种BGA焊球与具有下层电路层的叠层电路组件的外导电层的互连。本发明包括与外部导电层基本上共面的升高的BGA焊球垫，凸起垫具有凸起面和多个垂直导电壁以及具有大于凸起宽度的平均直径的BGA焊球 BGA焊球粘附到凸起面和垂直导电壁的大部分上。

5. 发明授权

US07253510B2 Ball grid array package construction with raised solder ball pads 有权
标题翻译：球栅阵列封装结构，凸起焊球垫
公开(公告)号：US07253510B2
公开(公告)日：2007-08-07
申请号：US10346277
申请日：2003-01-16
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L29/40 , H01L23/02 , H01L21/00 , H01L21/44 , H05K7/20 , H05K7/00 , H05K1/14 , H05K1/00 , H05K1/18
CPC分类号： H01L23/49816 , H01L25/0657 , H01L2224/16225 , H01L2225/06513 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K3/3457 , H05K3/4652 , H05K2201/098 , H05K2201/0989 , Y02P70/611 , H01L2224/0401
摘要： The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.
摘要翻译：本发明提供了一种BGA焊球与具有下层电路层的叠层电路组件的外导电层的互连。本发明包括与外部导电层基本上共面的升高的BGA焊球垫，凸起垫具有凸起面和多个垂直导电壁以及具有大于凸起宽度的平均直径的BGA焊球 BGA焊球粘附到凸起面和垂直导电壁的大部分上。

6. 发明授权

US06876088B2 Flex-based IC package construction employing a balanced lamination 失效
标题翻译：采用平衡层压的基于Flex的IC封装结构
公开(公告)号：US06876088B2
公开(公告)日：2005-04-05
申请号：US10346286
申请日：2003-01-16
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L23/32 , H01L25/065 , H05K1/02 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/40 , H05K3/46 , H01L23/48 , H01L23/02
CPC分类号： H05K1/0218 , H01L25/0657 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2225/06517 , H01L2225/06541 , H01L2225/06579 , H01L2924/00014 , H01L2924/09701 , H01L2924/3011 , H05K1/113 , H05K1/189 , H05K3/002 , H05K3/4007 , H05K3/4652 , H05K2201/0367 , H05K2201/0715 , H05K2201/10674 , H05K2203/0554 , H01L2224/05599
摘要： The present invention provides for a balanced laminated integrated circuit package. The package includes a two metal layer bumped circuit, a first adhesive layer having a thickness on a first side of the bumped circuit, a first outer conductive layer having a thickness bonded to the first adhesive layer and a second adhesive layer having a thickness substantially equal to the thickness of the first adhesive layer on a second side of the bumped circuit. The invention also includes a second outer conductive layer bonded to the second adhesive layer, the second outer conductive layer having a thickness substantially equal to the thickness of the first outer conductive layer.
摘要翻译：本发明提供一种平衡层叠集成电路封装。所述封装包括两个金属层凸起电路，在所述凸起电路的第一侧上具有厚度的第一粘合剂层，具有粘合到所述第一粘合剂层的厚度的第一外部导电层和具有基本上相等的厚度的第二粘合剂层相对于凸起电路的第二侧上的第一粘合剂层的厚度。本发明还包括结合到第二粘合剂层的第二外部导电层，第二外部导电层的厚度基本上等于第一外部导电层的厚度。

7. 发明授权

US06867121B2 Method of apparatus for interconnecting a relatively fine pitch circuit layer and adjacent power plane(s) in a laminated construction 失效
标题翻译：用于将层叠结构中的相对细间距电路层和相邻电力平面互连的方法和装置
公开(公告)号：US06867121B2
公开(公告)日：2005-03-15
申请号：US10346285
申请日：2003-01-16
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L23/498 , H05K3/06 , H05K3/40 , H05K3/46 , H01L21/44 , H01L21/4763
CPC分类号： H05K3/4038 , H01L23/49816 , H01L23/4985 , H01L2924/0002 , H05K3/064 , H05K3/4069 , H05K3/4652 , H05K2201/0305 , H05K2201/0352 , H05K2201/0367 , H05K2203/0554 , H05K2203/1476 , H01L2924/00
摘要： The present invention provides for a method of interconnecting a bumped circuit having relatively fine traces to an overlying conductive layer of a laminated circuit assembly. The overlying conductive layer is laminated with a suitable insulating adhesive over a bumped relatively fine pitch circuit layer. In the general vicinity of the desired power connection, a window substantially larger than the width of the bump is etched away from the conductive material of the trace of the outer conductive layer and the adhesive is plasma etched to expose the elevated portion of the desired bump of the bumped circuit. A conductive media such as conductive polymer or solder is then applied at the etched window of the overlying relatively coarse trace, which ensures an electrical connection between the exposed portion of the bump and the overlying trace.
摘要翻译：本发明提供了一种将具有相对精细迹线的凸起电路互连到层压电路组件的上覆导电层的方法。覆盖的导电层与凸起的相对细间距电路层上的合适的绝缘粘合剂层压。在所需功率连接的总体附近，基本上大于凸块的宽度的窗口被蚀刻远离外部导电层的迹线的导电材料，并且粘合剂被等离子体蚀刻以暴露所需凸块的升高部分的碰撞电路。导电介质如导电聚合物或焊料然后被施加在覆盖的相对粗糙的迹线的蚀刻窗口处，这确保凸起的暴露部分和上覆迹线之间的电连接。

8. 发明授权

US07816754B2 Ball grid array package construction with raised solder ball pads 有权
标题翻译：球栅阵列封装结构，凸起焊球垫
公开(公告)号：US07816754B2
公开(公告)日：2010-10-19
申请号：US11762479
申请日：2007-06-13
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L29/06 , H01L29/40
CPC分类号： H01L23/49816 , H01L25/0657 , H01L2224/16225 , H01L2225/06513 , H01L2225/06572 , H01L2225/06589 , H01L2924/00014 , H05K1/111 , H05K3/3436 , H05K3/3452 , H05K3/3457 , H05K3/4652 , H05K2201/098 , H05K2201/0989 , Y02P70/611 , H01L2224/0401
摘要： The present invention provides for a BGA solder ball interconnection to an outer conductive layer of a laminated circuit assembly having an underlying circuit layer. The invention includes a raised BGA solder ball pad substantially co-planar with the outer conductive layer, the raised pad having a raised face and a plurality of vertical conductive walls and a BGA solder ball having an average diameter of greater than the width of the raised face, the BGA solder ball being adhered to the raised face and to a substantial portion of the vertical conductive walls.
摘要翻译：本发明提供了一种BGA焊球与具有下层电路层的叠层电路组件的外导电层的互连。本发明包括与外部导电层基本上共面的升高的BGA焊球垫，凸起垫具有凸起面和多个垂直导电壁以及具有大于凸起宽度的平均直径的BGA焊球 BGA焊球粘附到凸起面和垂直导电壁的大部分上。

9. 发明授权

US5753976A Multi-layer circuit having a via matrix interlayer connection 失效
标题翻译：具有通孔矩阵层间连接的多层电路
公开(公告)号：US5753976A
公开(公告)日：1998-05-19
申请号：US663626
申请日：1996-06-14
申请人： Paul Marlan Harvey
发明人： Paul Marlan Harvey
IPC分类号： H01L23/12 , H05K1/11 , H05K3/40 , H05K3/42 , H05K3/46 , H05K1/00
CPC分类号： H05K1/115 , H05K3/42 , H05K2201/09781 , H05K2201/0979
摘要： An interlayer connection for electrically connecting first and second conductive elements and reducing interlayer registration requirements is disclosed. The interlayer connection includes a first layer including a first electrically conductive element, a second layer including a second electrically conductive element, and a third layer disposed between the first layer and the second layer. The third layer includes an electrically insulative portion having a matrix of immediately adjacent vias therethrough. A selected plurality of immediately adjacent vias within the matrix are disposed between the first and the second electrically conductive elements and contain electrically conductive material forming a conductive path between the first and the second electrically conductive elements.
摘要翻译：公开了用于电连接第一和第二导电元件并减少层间配准要求的层间连接。层间连接包括包括第一导电元件的第一层，包括第二导电元件的第二层和设置在第一层和第二层之间的第三层。第三层包括具有通过其直接相邻的通孔的矩阵的电绝缘部分。矩阵内的所选择的多个紧邻的通孔设置在第一和第二导电元件之间，并且包含在第一和第二导电元件之间形成导电路径的导电材料。

10. 发明授权

US07203608B1 Impedane measurement of chip, package, and board power supply system using pseudo impulse response 有权
标题翻译：使用伪冲击响应的芯片，封装和板电源系统的Impedane测量
公开(公告)号：US07203608B1
公开(公告)日：2007-04-10
申请号：US11424613
申请日：2006-06-16
申请人： Makoto Aikawa , Sang Hoo Dhong , Brian Flachs , Paul Marlan Harvey , Brad William Michael , Yaping Zhou
发明人： Makoto Aikawa , Sang Hoo Dhong , Brian Flachs , Paul Marlan Harvey , Brad William Michael , Yaping Zhou
IPC分类号： G01R27/28
CPC分类号： G01R27/16 , G01R27/205 , G01R31/3008
摘要： A method for measuring impedance of a microprocessor chip, electronic packaging, and circuit board power supply system by generating a pseudo-impulse current having a width size in the time domain not larger than the inversion of a maximum frequency of interest and obtaining a voltage measurement in a frequency domain of the pseudo-impulse current. The mechanism of the present invention then predicts the normalized Fourier transformation of the current in the frequency domain, wherein the normalized Fourier transformation depends upon a switching charge of the pseudo-impulse current, measures the switching charge of the pseudo-impulse current, obtains a first current measurement at zero frequency using the measured switching charge, and obtains a second current measurement at a frequency of interest using the first current measurement. The mechanism of the present invention then calculates the impedance of the chip/package/board power supply system using the voltage measurement and the second current measurement.
摘要翻译：一种用于测量微处理器芯片，电子封装和电路板电源系统的阻抗的方法，其通过产生具有不大于感兴趣的最大频率的反转的时域中的宽度尺寸的伪脉冲电流并获得电压测量在伪脉冲电流的频域中。然后，本发明的机构预测频域中的电流的归一化傅里叶变换，其中归一化傅里叶变换取决于伪脉冲电流的切换电荷，测量伪脉冲电流的开关电荷，获得使用测量的开关电荷在零频率下的第一电流测量，并且使用第一电流测量获得感兴趣频率的第二电流测量。然后，本发明的机构使用电压测量和第二电流测量来计算芯片/封装/板电源系统的阻抗。

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