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71. 发明申请

US20110173402A1 HARDWARE SUPPORT FOR COLLECTING PERFORMANCE COUNTERS DIRECTLY TO MEMORY 失效
标题翻译：硬件支持直接收集性能计数器
公开(公告)号：US20110173402A1
公开(公告)日：2011-07-14
申请号：US12684172
申请日：2010-01-08
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F12/16
CPC分类号： G06F11/348 , G06F2201/88
摘要： Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.
摘要翻译：在一个方面，在性能计数器直接收集到存储器的硬件支持可以包括多个性能计数器，可操作以收集一个或多个所选活动的一个或多个计数。第一存储元件可以用于存储存储器位置的地址。第二存储元件可以用于存储指示硬件是否应该开始复制的值。状态机可操作用于检测第二存储元件中的值，并且触发多个性能计数器中所选择的一个或多个性能计数器中的数据的硬件复制到其地址存储在第一存储元件中的存储单元。

72. 发明申请

US20120198118A1 USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY 失效
标题翻译：使用DMA将性能计数器数据复制到存储器
公开(公告)号：US20120198118A1
公开(公告)日：2012-08-02
申请号：US13446467
申请日：2012-04-13
申请人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
发明人： Alan Gara , Valentina Salapura , Robert W. Wisniewski
IPC分类号： G06F13/36
CPC分类号： G06F13/28 , G06F11/34 , G06F2201/88
摘要： A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data.
摘要翻译：用于复制性能计数器数据的设备包括将直接存储器访问（DMA）单元连接到多个硬件性能计数器和存储器设备的硬件路径。软件为DMA单元准备一个注入数据包来执行复制，而软件可以执行其他任务。在一个方面，准备注射分组的软件在收集硬件性能计数器数据的核心以外的处理核上运行。

73. 发明申请

US20060230239A1 Method and apparatus for detecting a cache wrap condition 有权
标题翻译：用于检测缓存包装条件的方法和装置
公开(公告)号：US20060230239A1
公开(公告)日：2006-10-12
申请号：US11093132
申请日：2005-03-29
申请人： Matthias Blumrich , Alan Gara , Mark Giampapa , Martin Ohmacht , Valentina Salapura
发明人： Matthias Blumrich , Alan Gara , Mark Giampapa , Martin Ohmacht , Valentina Salapura
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0831
摘要： A method and apparatus for detecting a cache wrap condition in a computing environment having a processor and a cache. A cache wrap condition is detected when the entire contents of a cache have been replaced, relative to a particular starting state. A set-associative cache is considered to have wrapped when all of the sets within the cache have been replaced. The starting point for cache wrap detection is the state of the cache sets at the time of the previous cache wrap. The method and apparatus is preferably implemented in a snoop filter having filter mechanisms that rely upon detecting the cache wrap condition. These snoop filter mechanisms requiring this information are operatively coupled with cache wrap detection logic adapted to detect the cache wrap event, and perform an indication step to the snoop filter mechanisms. In the various embodiments, cache wrap detection logic is implemented using registers and comparators, loadable counters, or a scoreboard data structure.
摘要翻译：一种用于在具有处理器和高速缓存的计算环境中检测高速缓存包装条件的方法和装置。当高速缓存的全部内容相对于特定的启动状态被替换时，检测到缓存包装条件。当缓存中的所有集合已被替换时，集合关联缓存被认为已被包装。高速缓存包检测的起始点是先前高速缓存包装时高速缓存集的状态。该方法和装置优选地在具有依赖于检测高速缓存包装条件的过滤机构的窥探过滤器中实现。这些需要该信息的窥探过滤机构可操作地与适用于检测高速缓存包裹事件的高速缓存包检测逻辑耦合，并且向窥探过滤机构执行指示步骤。在各种实施例中，使用寄存器和比较器，可加载计数器或记分板数据结构来实现高速缓存封包检测逻辑。

74. 发明授权

US08571834B2 Opcode counting for performance measurement 失效
公开(公告)号：US08571834B2
公开(公告)日：2013-10-29
申请号：US12688773
申请日：2010-01-15
申请人： Alan Gara , David L. Satterfield , Robert E. Walkup
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G21C17/00
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

75. 发明授权

US08327077B2 Method and apparatus of parallel computing with simultaneously operating stream prefetching and list prefetching engines 有权
标题翻译：并行计算的方法和装置，同时运行流预取和列表预取引擎
公开(公告)号：US08327077B2
公开(公告)日：2012-12-04
申请号：US12696746
申请日：2010-01-29
申请人： Peter A. Boyle , Norman H. Christ , Alan Gara , Robert D. Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter A. Boyle , Norman H. Christ , Alan Gara , Robert D. Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command.
摘要翻译：预取系统提高并行计算系统的性能。并行计算系统包括多个计算节点。计算节点包括至少一个处理器和至少一个存储器设备。预取系统包括至少一个流预取引擎和至少一个列表预取引擎。预取系统同时操作这些引擎。在至少一个处理器发出命令之后，预取系统将该命令传递给流预取引擎和列表预取引擎。预取系统操作流预取引擎和列预取引擎，以响应于传递的命令在处理器中的后续时钟周期中预取需要的数据。

76. 发明申请

US20110173398A1 TWO DIFFERENT PREFETCHING COMPLEMENTARY ENGINES OPERATING SIMULTANEOUSLY 有权
标题翻译：两个不同的预选辅助发动机同时运行
公开(公告)号：US20110173398A1
公开(公告)日：2011-07-14
申请号：US12696746
申请日：2010-01-29
申请人： Peter A. Boyle , Norman H. Christ , Alan Gara , Robert D. Mawhinney , Martin Ohmacht , Krishnan Sugavanam
发明人： Peter A. Boyle , Norman H. Christ , Alan Gara , Robert D. Mawhinney , Martin Ohmacht , Krishnan Sugavanam
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A prefetch system improves a performance of a parallel computing system. The parallel computing system includes a plurality of computing nodes. A computing node includes at least one processor and at least one memory device. The prefetch system includes at least one stream prefetch engine and at least one list prefetch engine. The prefetch system operates those engines simultaneously. After the at least one processor issues a command, the prefetch system passes the command to a stream prefetch engine and a list prefetch engine. The prefetch system operates the stream prefetch engine and the list prefetch engine to prefetch data to be needed in subsequent clock cycles in the processor in response to the passed command.
摘要翻译：预取系统提高并行计算系统的性能。并行计算系统包括多个计算节点。计算节点包括至少一个处理器和至少一个存储器设备。预取系统包括至少一个流预取引擎和至少一个列表预取引擎。预取系统同时操作这些引擎。在至少一个处理器发出命令之后，预取系统将该命令传递给流预取引擎和列表预取引擎。预取系统操作流预取引擎和列预取引擎，以响应于传递的命令在处理器中的后续时钟周期中预取需要的数据。

77. 发明申请

US20110172969A1 OPCODE COUNTING FOR PERFORMANCE MEASUREMENT 失效
标题翻译：用于性能测量的操作码计数
公开(公告)号：US20110172969A1
公开(公告)日：2011-07-14
申请号：US12688773
申请日：2010-01-15
申请人： Alan Gara , David L. Satterfield , Robert E. Walkup
发明人： Alan Gara , David L. Satterfield , Robert E. Walkup
IPC分类号： G06F15/00
CPC分类号： G06F9/30021 , G06F9/3001 , G06F9/30018 , G06F9/30145 , G06F11/3024 , G06F11/3409 , G06F11/348 , G06F15/17362 , G06F15/17381 , G06F15/17393 , G06F2201/88 , H04L67/10
摘要： Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.
摘要翻译：公开了用于测量在处理系统的处理单元上运行的程序的性能的方法，系统和计算机程序产品。在一个实施例中，该方法包括通知处理单元执行的程序中的每个指令的逻辑单元，向每个指令分配权重，将指令分配给多个组，以及分析多个组以测量一个或更多指标。在一个实施例中，每个指令包括操作代码部分，并且分配包括基于指令的操作代码部分将指令分配给组。在一个实施例中，每种类型的指令被分配给多个组中的相应一个组。这些组可以组合成多个组的组。

78. 发明授权

US08117288B2 Optimizing layout of an application on a massively parallel supercomputer 失效
标题翻译：在大型并行超级计算机上优化应用程序的布局
公开(公告)号：US08117288B2
公开(公告)日：2012-02-14
申请号：US10963101
申请日：2004-10-12
申请人： Gyan V. Bhanot , Alan Gara , Philip Heidelberger , Eoin M. Lawless , James C. Sexton , Robert E. Walkup
发明人： Gyan V. Bhanot , Alan Gara , Philip Heidelberger , Eoin M. Lawless , James C. Sexton , Robert E. Walkup
IPC分类号： G06F15/177
CPC分类号： G06F9/5066
摘要： A general computer-implement method and apparatus to optimize problem layout on a massively parallel supercomputer is described. The method takes as input the communication matrix of an arbitrary problem in the form of an array whose entries C(i, j) are the amount to data communicated from domain i to domain j. Given C(i, j), first implement a heuristic map is implemented which attempts sequentially to map a domain and its communications neighbors either to the same supercomputer node or to near-neighbor nodes on the supercomputer torus while keeping the number of domains mapped to a supercomputer node constant (as much as possible). Next a Markov Chain of maps is generated from the initial map using Monte Carlo simulation with Free Energy (cost function) F=Σi,jC(i,j)H(i,j)− where H(i,j) is the smallest number of hops on the supercomputer torus between domain i and domain j. On the cases tested, found was that the method produces good mappings and has the potential to be used as a general layout optimization tool for parallel codes. At the moment, the serial code implemented to test the method is un-optimized so that computation time to find the optimum map can be several hours on a typical PC. For production implementation, good parallel code for our algorithm would be required which could itself be implemented on supercomputer.
摘要翻译：描述了在大型并行超级计算机上优化问题布局的通用计算机实现方法和装置。该方法采用数组形式的任意问题的通信矩阵作为输入，其条目C（i，j）是从域i到域j传送的数据量。给定C（i，j），首先实现启发式映射，其尝试顺序地将域及其通信邻居映射到超级计算机节点或超级计算机环面上的近邻节点，同时保持域的数量映射到超级计算机节点常数（尽可能多）。接下来，使用具有自由能的蒙特卡罗模拟（成本函数）F =＆Sgr; i，jC（i，j）H（i，j），从初始映射生成马尔科夫链映射。其中H（i，j）域i和域j之间的超级计算机环面上的最小跳数。在测试的情况下，发现该方法产生良好的映射，并且有可能被用作并行代码的通用布局优化工具。此时，实现测试方法的序列号未优化，以便在典型的PC上找到最佳映射的计算时间可以为几个小时。对于生产实现，将需要我们的算法的良好的并行代码，这本身可以在超级计算机上实现。

79. 发明授权

US07701846B2 Bad data packet capture device 失效
标题翻译：坏数据包捕获设备
公开(公告)号：US07701846B2
公开(公告)日：2010-04-20
申请号：US11768572
申请日：2007-06-26
申请人： Dong Chen , Alan Gara , Philip Heidelberger , Pavlos Vranas
发明人： Dong Chen , Alan Gara , Philip Heidelberger , Pavlos Vranas
IPC分类号： H04L1/00
CPC分类号： H04L43/0847
摘要： An apparatus and method for capturing data packets for analysis on a network computing system includes a sending node and a receiving node connected by a bi-directional communication link. The sending node sends a data transmission to the receiving node on the bi-directional communication link, and the receiving node receives the data transmission and verifies the data transmission to determine valid data and invalid data and verify retransmissions of invalid data as corresponding valid data. A memory device communicates with the receiving node for storing the invalid data and the corresponding valid data. A computing node communicates with the memory device and receives and performs an analysis of the invalid data and the corresponding valid data received from the memory device.
摘要翻译：用于捕获数据分组以用于在网络计算系统上进行分析的装置和方法包括通过双向通信链路连接的发送节点和接收节点。发送节点向双向通信链路上的接收节点发送数据传输，接收节点接收数据传输，验证数据传输，确定有效数据和无效数据，并验证无效数据的重传是对应的有效数据。存储装置与接收节点进行通信，用于存储无效数据和对应的有效数据。计算节点与存储器件进行通信，并且接收并执行从存储器件接收的无效数据和对应的有效数据的分析。

80. 发明申请

US20120210172A1 MULTIPROCESSOR SWITCH WITH SELECTIVE PAIRING 失效
标题翻译：具有选择性配对的多处理器开关
公开(公告)号：US20120210172A1
公开(公告)日：2012-08-16
申请号：US13027882
申请日：2011-02-15
申请人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
发明人： Alan Gara , Michael Karl Gschwind , Valentina Salapura
IPC分类号： G06F11/07
CPC分类号： G06F11/1641 , G06F11/1654 , G06F2201/845
摘要： System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.
摘要翻译：用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设设备等。存储器套件通过开关或总线连接到选择性配对设施。

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