专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明申请

US20120132992A1 SEMICONDUCTOR STRUCTURE INCLUDING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON AN SOI SUBSTRATE 有权
标题翻译：在SOI衬底上包括高性能FET和高电压FET的半导体结构
公开(公告)号：US20120132992A1
公开(公告)日：2012-05-31
申请号：US13367646
申请日：2012-02-07
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L27/12
CPC分类号： H01L27/088 , H01L21/823462 , H01L21/823481 , H01L27/1207
摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.
摘要翻译：第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。还提供了用于半导体结构的设计结构。

72. 发明授权

US08022496B2 Semiconductor structure and method of manufacture 有权
标题翻译：半导体结构及制造方法
公开(公告)号：US08022496B2
公开(公告)日：2011-09-20
申请号：US11873696
申请日：2007-10-17
申请人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Alvin J. Joseph , Seong-dong Kim , Louis D. Lanzerotti , Xuefeng Liu , Robert M. Rassel
IPC分类号： H01L29/47
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

73. 发明申请

US20110102537A1 Thermal printing with laser activation 审中-公开
标题翻译：激光激光热敏打印
公开(公告)号：US20110102537A1
公开(公告)日：2011-05-05
申请号：US11596734
申请日：2005-05-19
申请人： Neil Griffin , Samuel Charles William Hyde , Anthony Hailes , Keith Turner , Nicholas James Wooder , John Haig Marsh , Stephen Gorton , Christopher Humby , Gary Ternent , Eric Goutain , Xuefeng Liu , Alexander Ballantyne
发明人： Neil Griffin , Samuel Charles William Hyde , Anthony Hailes , Keith Turner , Nicholas James Wooder , John Haig Marsh , Stephen Gorton , Christopher Humby , Gary Ternent , Eric Goutain , Xuefeng Liu , Alexander Ballantyne
IPC分类号： B41J2/435
CPC分类号： H04N1/40031 , B41J2/45 , B41J2/4753 , H01S5/06804 , H01S5/4025 , H04N1/1932 , H04N1/1934 , H04N1/40043 , H04N1/4005
摘要： Methods and apparatus for implementing thermal printing techniques onto thermally sensitive print media use one or more laser arrays to provide optical heating. Thermal management of the laser arrays is described. Techniques for alignment of multiple monolithic arrays onto a common carrier are described. Various output optics are described.
摘要翻译：在热敏打印介质上实施热敏打印技术的方法和设备使用一个或多个激光阵列来提供光学加热。描述了激光阵列的热管理。描述了将多个单片阵列对准到公共载体上的技术。描述各种输出光学器件。

74. 发明申请

US20100035390A1 METHOD OF FORMING A HIGH PERFORMANCE FET AND A HIGH VOLTAGE FET ON A SOI SUBSTRATE 有权
标题翻译：在SOI衬底上形成高性能FET和高电压FET的方法
公开(公告)号：US20100035390A1
公开(公告)日：2010-02-11
申请号：US12188366
申请日：2008-08-08
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu , Yun Shi
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823462 , H01L21/823481 , H01L27/1203 , H01L27/1207
摘要： A first portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate is protected, while a second portion of the top semiconductor layer is removed to expose a buried insulator layer. A first field effect transistor including a gate dielectric and a gate electrode located over the first portion of the top semiconductor layer is formed. A portion of the exposed buried insulator layer is employed as a gate dielectric for a second field effect transistor. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer.
摘要翻译：保护绝缘体上半导体（SOI）衬底的顶部半导体层的第一部分，同时去除顶部半导体层的第二部分以暴露掩埋的绝缘体层。形成包括位于顶部半导体层的第一部分上方的栅极电介质和栅电极的第一场效应晶体管。暴露的掩埋绝缘体层的一部分用作第二场效应晶体管的栅极电介质。在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。

75. 发明申请

US20090317975A1 METHOD FOR FORMING AN 0N-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
标题翻译：用于形成0N芯片高频电静电放电装置的方法
公开(公告)号：US20090317975A1
公开(公告)日：2009-12-24
申请号：US12144071
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/311
CPC分类号： H01L21/7682 , H01L21/3148 , H01L21/318 , H01L21/3185 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided and a hermetically sealed gap is formed therein to provide electro-static discharge protection for an integrated circuit.
摘要翻译：描述形成片上高频静电放电装置的方法。在一个实施例中，提供具有多金属水平布线的晶片，并且在其中形成气密密封的间隙以为集成电路提供静电放电保护。

76. 发明申请

US20090317970A1 METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
标题翻译：用于形成片上高频电静电放电装置的方法
公开(公告)号：US20090317970A1
公开(公告)日：2009-12-24
申请号：US12144089
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/7682 , H01L27/0248
摘要： A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection.
摘要翻译：描述了在集成电路上形成片上高频静电放电装置的方法。在该方法的一个实施例中，提供了一种其上形成有多于一个电极的封盖的第一电介质层。在封盖的第一介电层上沉积第二介电层。第一硬掩模介电层沉积在第二介电层上。通过第一硬掩模电介质层和第二电介质层形成腔沟槽到第一介电层，其中在两个相邻电极之间的第一电介质层中形成空腔沟槽。至少一个通孔围绕腔沟槽形成穿过第二电介质层。在所述至少一个通孔中的每一个周围形成金属沟槽。在空腔沟槽上形成释放开口。在第二电介质层上沉积第三电介质层，其中第三介电层气密地密封释放开口以提供静电放电保护。

77. 发明申请

US20090316314A1 DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 有权
标题翻译：片上高频电子放电装置的设计结构
公开(公告)号：US20090316314A1
公开(公告)日：2009-12-24
申请号：US12144095
申请日：2008-06-23
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu , Anthony K. Stamper
IPC分类号： H02H9/00 , G06F17/50
CPC分类号： H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge structure comprises a first dielectric layer with more than one electrode formed therein. A second dielectric layer with more than one electrode formed therein is located above the first dielectric layer. At least one via connects the more than one electrode in the first dielectric layer with the more than one electrode in the second dielectric layer. A gap is formed through the first dielectric layer and the second dielectric layer, wherein the gap extends between two adjacent electrodes in both the first dielectric layer and the second dielectric layer. A third dielectric layer is disposed over the second dielectric layer, wherein the third dielectric layer hermetically seals the gap to provide electro-static discharge protection on the integrated circuit.
摘要翻译：描述了片上高频静电放电装置的设计结构。在一个实施例中，静电放电结构包括其中形成有多于一个电极的第一电介质层。其中形成有多于一个电极的第二电介质层位于第一介电层的上方。至少一个通孔将第一介电层中的多于一个的电极与第二介电层中的多于一个的电极连接。通过第一电介质层和第二电介质层形成间隙，其中间隙在第一电介质层和第二电介质层中的两个相邻电极之间延伸。第三电介质层设置在第二电介质层上，其中第三介电层气密地密封间隙以在集成电路上提供静电放电保护。

78. 发明授权

US07564319B2 Vertical LC tank device 失效
标题翻译：垂直液相色谱槽装置
公开(公告)号：US07564319B2
公开(公告)日：2009-07-21
申请号：US11859850
申请日：2007-09-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H03B5/08 , H01F5/00 , H01L29/00
CPC分类号： H03L7/099 , H01L23/5223 , H01L23/5225 , H01L23/5227 , H01L27/0617 , H01L27/0641 , H01L27/08 , H01L27/0811 , H01L28/10 , H01L2924/0002 , H03J3/20 , H01L2924/00
摘要： An LC tack structure. The structure, including a set of wiring levels on top of a semiconductor substrate, the wiring levels stacked on top of each other from a lowest wiring level nearest the substrate to a highest wiring level furthest from the substrate; an inductor in the highest wiring level, the inductor confined within a perimeter of a region of the highest wiring level; and a varactor formed in the substrate, the varactor aligned completely under the perimeter of the region of the highest wiring level. The structure may additionally include an electric shield in a wiring level of the set of wiring levels between the lowest wiring level and the highest wiring level. Alternatively, the inductor includes a magnetic core and alternating electrically non-magnetic conductive metal coils and magnetic coils around the core.
摘要翻译：一种LC粘结结构。该结构包括在半导体衬底顶部的一组布线级别，从最靠近衬底的最低配线水平到离衬底最远的最高配线电平彼此堆叠的布线电平; 电感处于最高布线水平，电感器限制在最高布线水平的区域的周边内; 以及形成在基板中的变容二极管，变容二极管完全对准在最高布线水平的区域的周边。该结构可以另外包括在最低布线电平和最高布线电平之间的布线级别的布线级中的电屏蔽。或者，电感器包括磁芯和交替的非磁性导电金属线圈和围绕磁芯的磁性线圈。

79. 发明申请

US20090026912A1 INTENSITY MODULATED ELECTRON BEAM AND APPLICATION TO ELECTRON BEAM BLANKER 审中-公开
标题翻译：强度调制电子束和应用于电子束保护膜
公开(公告)号：US20090026912A1
公开(公告)日：2009-01-29
申请号：US11829034
申请日：2007-07-26
申请人： Vincenzo Lordi , Kirkwood Rough , Xuefeng Liu , Shem-Tov Levi
发明人： Vincenzo Lordi , Kirkwood Rough , Xuefeng Liu , Shem-Tov Levi
IPC分类号： H01J37/302 , H01J29/51 , H01J37/30
CPC分类号： H01J37/063 , B82Y10/00 , B82Y40/00 , H01J37/045 , H01J37/073 , H01J37/075 , H01J37/3174 , H01J2237/0432
摘要： Method and apparatus for achieving an intensity modulated electron blanker are disclosed. An apparatus includes a cathode exposed to an activation source to generate an electron beam. Cathode control circuitry adjusts a cathode control amplifier to regulate cathode voltage and the potential of the electron beam. In some approaches the electron beam potential is used to control the blanking frequency, switching speeds, and duty cycle. In another approach electron generating beams directed on to the cathode are modulated to control the electron beam.
摘要翻译：公开了用于实现强度调制的电子消除器的方法和装置。一种装置包括暴露于激活源的阴极以产生电子束。阴极控制电路调节阴极控制放大器以调节阴极电压和电子束的电位。在一些方法中，电子束电位用于控制消隐频率，开关速度和占空比。在另一种方法中，调节指向阴极的电子产生光束以控制电子束。

80. 发明申请

US20080142861A1 SYMMETRIC CAPACITOR STRUCTURE 审中-公开
标题翻译：对称电容结构
公开(公告)号：US20080142861A1
公开(公告)日：2008-06-19
申请号：US12029748
申请日：2008-02-12
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/94
CPC分类号： H01L27/0805
摘要： A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：一种包括形成在衬底内的第一掺杂区，第二掺杂区，第三掺杂区和第一浅沟槽隔离结构的结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式