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1. 发明申请

US20080142861A1 SYMMETRIC CAPACITOR STRUCTURE 审中-公开
标题翻译：对称电容结构
公开(公告)号：US20080142861A1
公开(公告)日：2008-06-19
申请号：US12029748
申请日：2008-02-12
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/94
CPC分类号： H01L27/0805
摘要： A structure comprising a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：一种包括形成在衬底内的第一掺杂区，第二掺杂区，第三掺杂区和第一浅沟槽隔离结构的结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

2. 发明授权

US07402890B2 Method for symmetric capacitor formation 有权
标题翻译：对称电容器形成方法
公开(公告)号：US07402890B2
公开(公告)日：2008-07-22
申请号：US11421774
申请日：2006-06-02
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/00
CPC分类号： H01L27/0805
摘要： A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：用于形成结构的结构和相关联的方法。该结构包括形成在衬底内的第一掺杂区域，第二掺杂区域，第三掺杂区域和第一浅沟槽隔离结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

3. 发明申请

US20070278618A1 METHOD AND STRUCTURE FOR SYMMETRIC CAPACITOR FORMATION 有权
标题翻译：对称电容器形成的方法和结构
公开(公告)号：US20070278618A1
公开(公告)日：2007-12-06
申请号：US11421774
申请日：2006-06-02
申请人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
发明人： David S. Collins , Hanyi Ding , Kai Di Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： H01L29/00
CPC分类号： H01L27/0805
摘要： A structure and associated method for forming a structure. The structure comprises a first doped region, a second doped region, a third doped region, and a first shallow trench isolation structure formed within a substrate. The first doped region comprises a first dopant having a first polarity. The second doped region forms a first electrode of a capacitor. The third doped region forms a second electrode of the capacitor. Each of the second doped region and the third doped region comprises a second dopant having a second polarity. The first shallow trench isolation structure is formed between the second doped region and the third doped region. The capacitor comprises a main capacitance. The structure comprises a first parasitic capacitance and a second parasitic capacitance. The first parasitic capacitance is about equal to the second parasitic capacitance.
摘要翻译：用于形成结构的结构和相关联的方法。该结构包括形成在衬底内的第一掺杂区域，第二掺杂区域，第三掺杂区域和第一浅沟槽隔离结构。第一掺杂区域包括具有第一极性的第一掺杂剂。第二掺杂区域形成电容器的第一电极。第三掺杂区域形成电容器的第二电极。第二掺杂区域和第三掺杂区域中的每一个包括具有第二极性的第二掺杂剂。第一浅沟槽隔离结构形成在第二掺杂区和第三掺杂区之间。电容器包括主电容。该结构包括第一寄生电容和第二寄生电容。第一寄生电容约等于第二寄生电容。

4. 发明授权

US08674423B2 Semiconductor structure having vias and high density capacitors 有权
标题翻译：具有通孔和高密度电容器的半导体结构
公开(公告)号：US08674423B2
公开(公告)日：2014-03-18
申请号：US13302168
申请日：2011-11-22
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L27/108
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译：制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。第一和第二沟槽在衬底中具有不同的深度。

5. 发明授权

US08101494B2 Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors 有权
标题翻译：具有VIAS和高密度电容器结构的结构，设计结构和方法
公开(公告)号：US08101494B2
公开(公告)日：2012-01-24
申请号：US12191379
申请日：2008-08-14
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译：制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。第一和第二沟槽在衬底中具有不同的深度。

6. 发明申请

US20100041203A1 Structure, Design Structure and Method of Manufacturing a Structure Having VIAS and High Density Capacitors 有权
标题翻译：具有VIAS和高密度电容器的结构，设计结构和制造方法
公开(公告)号：US20100041203A1
公开(公告)日：2010-02-18
申请号：US12191379
申请日：2008-08-14
申请人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
发明人： David S. Collins , Kai D. Feng , Zhong-Xiang He , Peter J. Lindgren , Robert M. Rassel
IPC分类号： H01L21/20
CPC分类号： H01L29/945 , H01L23/481 , H01L23/5223 , H01L23/642 , H01L29/66181 , H01L2924/0002 , H01L2924/00
摘要： A method of making a semiconductor structure includes forming at least a first trench and a second trench having different depths in a substrate, forming a capacitor in the first trench, and forming a via in the second trench. A semiconductor structure includes a capacitor arranged in a first trench formed in a substrate and a via arranged in a second trench formed in the substrate. The first and second trenches have different depths in the substrate.
摘要翻译：制造半导体结构的方法包括在衬底中形成至少具有不同深度的第一沟槽和第二沟槽，在第一沟槽中形成电容器，并在第二沟槽中形成通孔。半导体结构包括布置在形成在衬底中的第一沟槽中的电容器和布置在形成于衬底中的第二沟槽中的通孔。第一和第二沟槽在衬底中具有不同的深度。

7. 发明申请

US20080149983A1 METAL-OXIDE-SEMICONDUCTOR (MOS) VARACTORS AND METHODS OF FORMING MOS VARACTORS 审中-公开
标题翻译：金属氧化物半导体（MOS）变压器及形成MOS电容器的方法
公开(公告)号：US20080149983A1
公开(公告)日：2008-06-26
申请号：US11613471
申请日：2006-12-20
申请人： Robert Mark Rassel , Douglas Duane Coolbaugh , Zhong-Xiang He , Ebenezer E. Eshun , David S. Collins , Douglas Brian Hershberger
发明人： Robert Mark Rassel , Douglas Duane Coolbaugh , Zhong-Xiang He , Ebenezer E. Eshun , David S. Collins , Douglas Brian Hershberger
IPC分类号： H01L29/94 , H01L21/20 , H01L21/336
CPC分类号： H01L29/93 , H01L29/94
摘要： MOS varactor having an entire accumulation and depletion regime of its CV characteristic curve in one bias regime (negative or positive). The MOS varactor may comprise a gate electrode, a well region of semiconductor material having a first conductivity type (e.g., p-type), contact regions to the well region that comprise heavily doped semiconductor material of the first conductivity type (e.g., p+-type), and a Schottky junction formed between the gate and contact regions. The Schottky junction may be formed by spacing the contact regions away from the gate electrode and siliciding the substrate surface. The gate electrode may be formed from semiconductor material of a second conductivity type (e.g., n-type) opposite to the first conductivity type, thus changing the flat band voltage of the MOS varactor and shifting accumulation and depletion regime of the CV characteristic curve in one bias regime, such as the negative bias regime.
摘要翻译： MOS变容二极管在一个偏置方式（负或正）中具有其CV特性曲线的整体累积和耗尽方式。 MOS变容二极管可以包括栅电极，具有第一导电类型（例如，p型）的半导体材料的阱区，包括第一导电类型的重掺杂半导体材料的阱区的接触区域（例如，p < SUP + +型）和在栅极和接触区域之间形成的肖特基结。肖特基结可以通过将接触区域与栅电极隔开并使衬底表面硅化而形成。栅电极可以由与第一导电类型相反的第二导电类型（例如，n型）的半导体材料形成，从而改变MOS变容二极管的平带电压以及CV特性曲线的转移累积和耗尽状态一种偏见制度，如负偏见制度。

8. 发明授权

US07868423B2 Optimized device isolation 有权
标题翻译：优化设备隔离
公开(公告)号：US07868423B2
公开(公告)日：2011-01-11
申请号：US12269073
申请日：2008-11-12
申请人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St. Onge , James A. Slinkman
发明人： John J. Benoit , David S. Collins , Natalie B. Feilchenfeld , Michael L. Gautsch , Xuefeng Liu , Robert M. Rassel , Stephen A. St. Onge , James A. Slinkman
IPC分类号： H01L21/02
CPC分类号： H01L21/761 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0921 , H01L27/0928
摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.
摘要翻译：用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。隔离MOSFET的n阱连接到深n波段区域。所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

9. 发明授权

US08288244B2 Lateral passive device having dual annular electrodes 有权
标题翻译：具有双环形电极的横向无源器件
公开(公告)号：US08288244B2
公开(公告)日：2012-10-16
申请号：US12835283
申请日：2010-07-13
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A method for forming a lateral passive device including a dual annular electrode is disclosed. The annular electrodes formed from the method include an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced.
摘要翻译：公开了一种用于形成包括双环形电极的横向无源器件的方法。由该方法形成的环形电极包括阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。

10. 发明申请

US20100279483A1 LATERAL PASSIVE DEVICE HAVING DUAL ANNULAR ELECTRODES 有权
标题翻译：具有双重电极的侧向被动装置
公开(公告)号：US20100279483A1
公开(公告)日：2010-11-04
申请号：US12835283
申请日：2010-07-13
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/329 , H01L21/04
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.
摘要翻译：公开了一种包括双环形电极的横向无源器件。环形电极形成阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。在一个实施例中，装置包括围绕形成在基板上的第二环形电极的第一环形电极，并且第二环形电极围绕绝缘体区域。还公开了相关方法。

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