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71. 发明申请

US20110318865A1 MANUFACTURING PROCESS FOR MAKING PHOTOVOLTAIC SOLAR CELLS 失效
标题翻译：制造光伏太阳能电池的制造工艺
公开(公告)号：US20110318865A1
公开(公告)日：2011-12-29
申请号：US13154140
申请日：2011-06-06
申请人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
发明人： Ranier Krauser , Lawrence A. Clevenger , Kevin Prettyman , Brian Christopher Sapp , Kevin S. Petrarca , Harold John Hovel , Gerd Pfeiffer , Zhengwen Li , Carl John Radens
IPC分类号： H01L31/18
CPC分类号： H01L31/1804 , H01L31/02167 , H01L31/022425 , H01L31/068 , Y02E10/547 , Y02P70/521
摘要： The invention relates to a manufacturing process of a photovoltaic solar cell (100) comprising: providing high doped areas (20) on the rear side (18) of the photovoltaic solar cell (100), providing localized metal contacts (30) localized on said high doped areas (20), providing a passivation layer (50) covering a surface (52) between said contacts (30), wherein the contacts (30) remain substantially free of the passivation layer (50), and depositing a metal layer (32) for a back surface field.
摘要翻译：本发明涉及一种光伏太阳能电池（100）的制造方法，包括：在光伏太阳能电池（100）的后侧（18）上提供高掺杂区域（20），提供位于所述光伏太阳能电池（100）上的局部金属触点（30）提供覆盖所述触头（30）之间的表面（52）的钝化层（50），其中触点（30）保持基本上不含钝化层（50），并沉积金属层（50） 32）用于背面场。

72. 发明申请

US20110092069A1 SELF-ALIGNED PATTERNED ETCH STOP LAYERS FOR SEMICONDUCTOR DEVICES 失效
标题翻译：用于半导体器件的自对准图形蚀刻停止层
公开(公告)号：US20110092069A1
公开(公告)日：2011-04-21
申请号：US12582137
申请日：2009-10-20
申请人： Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
发明人： Kangguo Cheng , Lawrence A. Clevenger , Johnathan E. Faltermeier , Stephan Grunow , Kaushik A. Kumar , Kevin S. Petrarca
IPC分类号： H01L21/3205 , H01L21/768
CPC分类号： H01L21/76808 , H01L21/76802 , H01L21/7681 , H01L21/76825 , H01L21/76829
摘要： A method of forming a semiconductor device includes patterning a photoresist layer formed over a homogeneous semiconductor device layer to be etched; subjecting the semiconductor device to an implant process that selectively implants a sacrificial etch stop layer that is self-aligned in accordance with locations of features to be etched within the homogeneous semiconductor device layer, and at a desired depth for the features to be etched; etching a feature pattern defined by the patterned photoresist layer into the homogenous semiconductor device layer, stopping on the implanted sacrificial etch stop layer; and removing remaining portion of the implanted sacrificial etch stop layer prior to filling the etched feature pattern with a fill material.
摘要翻译：形成半导体器件的方法包括：图案化在待蚀刻的均匀半导体器件层上形成的光致抗蚀剂层; 对半导体器件进行注入工艺，该注入工艺根据待均匀半导体器件层内待蚀刻的特征的位置以及在要蚀刻的特征的期望深度选择性地埋入自对准的牺牲蚀刻停止层; 将由图案化的光致抗蚀剂层限定的特征图案蚀刻成均匀的半导体器件层，停止在注入的牺牲蚀刻停止层上; 以及在用填充材料填充蚀刻的特征图案之前去除注入的牺牲蚀刻停止层的剩余部分。

73. 发明申请

US20110045644A1 FUSE LINK STRUCTURES USING FILM STRESS FOR PROGRAMMING AND METHODS OF MANUFACTURE 有权
公开(公告)号：US20110045644A1
公开(公告)日：2011-02-24
申请号：US12939538
申请日：2010-11-04
申请人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
发明人： Karl W. Barth , Jeffrey P. Gambino , Tom C. Lee , Kevin S. Petrarca
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a programmable fuse structure includes forming at least one shallow trench isolation (STI) in a substrate, forming an e-fuse over the at least one STI and depositing an interlevel dielectric (ILD) layer over the e-fuse. Additionally, the method includes removing at least a portion of the at least one STI under the e-fuse to provide an air gap below a portion of the e-fuse and removing at least a portion of the ILD layer over the e-fuse to provide the air gap above the portion of the e-fuse.

74. 发明申请

US20110037143A1 Semiconductor Device Using An Aluminum Interconnect To Form Through-Silicon Vias 失效
标题翻译：使用铝互连形成通硅通孔的半导体器件
公开(公告)号：US20110037143A1
公开(公告)日：2011-02-17
申请号：US12539105
申请日：2009-08-11
申请人： Kevin S. Petrarca , Matthew Angyal , Lawrence A. Clevenger , Carl Radens , Brian C. Sapp
发明人： Kevin S. Petrarca , Matthew Angyal , Lawrence A. Clevenger , Carl Radens , Brian C. Sapp
IPC分类号： H01L29/92 , H01L23/48 , H01L21/02 , H01L21/768
CPC分类号： H01L21/76898 , H01L21/76895 , H01L23/481 , H01L23/5222 , H01L28/60 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： An aluminum lateral interconnect of a Back End of the Line (BEOL) is used to define the x and y dimensions of a through-silicon via in a semiconductor chip formed in a silicon substrate. The TSV includes one or more aluminum annulus formed on a surface of the substrate, and a deep trench in the substrate having a diameter that is determined by the diameter of the aluminum annulus. The annulus can also be provided with a conductive strap upon which a capacitor can be formed. The strap can also be used to provide a connection of the TV to other BEOL interconnects.
摘要翻译：线的后端（BEOL）的铝横向互连用于在形成于硅衬底中的半导体芯片中限定穿硅通孔的x和y尺寸。 TSV包括形成在基板的表面上的一个或多个铝环，以及基板中的深沟槽，其直径由铝环的直径决定。环也可以设置有可以形成电容器的导电带。带子也可用于提供电视与其他BEOL互连的连接。

75. 发明授权

US07534696B2 Multilayer interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US07534696B2
公开(公告)日：2009-05-19
申请号：US11429708
申请日：2006-05-08
申请人： Christopher V. Jahnes , Satyanarayana V. Nitta , Kevin S. Petrarca , Katherine L. Saenger
发明人： Christopher V. Jahnes , Satyanarayana V. Nitta , Kevin S. Petrarca , Katherine L. Saenger
IPC分类号： H01L21/76
CPC分类号： H01L21/7682 , H01L21/76808 , H01L21/76831 , H01L21/76835 , H01L23/5222 , H01L23/53295 , H01L2221/1026 , H01L2221/1031 , H01L2924/0002 , H01L2924/00
摘要： A multilevel air-gap-containing interconnect structure and a method of fabricating the same are provided. The multilevel air-gap-containing interconnect structure includes a collection of interspersed line levels and via levels, with via levels comprising conductive vias embedded in one or more dielectric layers in which the dielectric layers are solid underneath and above line features in adjacent levels, and perforated between line features. The line levels contain conductive lines and an air-gap-containing dielectric. A solid dielectric bridge layer, containing conductive contacts and formed by filling in a perforated dielectric layer, is disposed over the collection of interspersed line and via levels.
摘要翻译：提供了一种具有多级气隙的互连结构及其制造方法。多层含气隙的互连结构包括散布的线电平和通孔电平的集合，其中通孔层包括嵌入在一个或多个电介质层中的导电通孔，其中电介质层在相邻电平之下的电极特征和固定电极层之上，以及线之间穿孔特征。线路电平包含导电线和含气隙的电介质。包含导电接触并通过填充有孔电介质层形成的固体介质桥接层设置在散布的线路和通孔层的集合上。

76. 发明申请

US20080286660A1 DAMASCENE RETICLE AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：大理石制品及其制造方法
公开(公告)号：US20080286660A1
公开(公告)日：2008-11-20
申请号：US11749384
申请日：2007-05-16
申请人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
发明人： Kevin S. Petrarca , Donald F. Canaperi , Mahadevaiyer Krishnan , Rebecca D. Mih , Steven Steen , Henry Grabarz , Michael S. Hibbs
IPC分类号： G03F1/00 , C09K3/14
CPC分类号： G03F1/00 , G03F1/26 , G03F1/50
摘要： A method for manufacturing an optical projection reticle employs a damascene process. First feature recesses are etched into a projection reticle mask plate which is transmissive or transparent. Then feature recesses are tilled with a radiation transmissivity modifying material comprising a partially transmissive material and/or a radiation absorber for absorbing actinic radiation. Sacrificial materials may be added to the recess temporarily prior to filling the recess to provide gaps juxtaposed with the material filling the recess. Thereafter, the sacrificial materials are removed. Then the projection mask is planarized leaving feature recesses filled with transmissivity modifying material, and any gaps desired. The projection mask is planarized while retained in a fixture holding it in place during polishing with a polishing tool and a slurry.
摘要翻译：光学投影掩模版的制造方法采用镶嵌工艺。第一特征凹槽被蚀刻到透射或透明的突出掩模掩模板中。然后，特征凹部用包括用于吸收光化辐射的部分透射材料和/或辐射吸收体的辐射透射率改性材料研磨。牺牲材料可以在填充凹部之前临时添加到凹部中，以提供与填充凹部的材料并置的间隙。此后，去除牺牲材料。然后将投影掩模平坦化，留下填充有透射率改性材料的特征凹部，以及任何期望的间隙。投影面罩被平坦化，同时保持在用抛光工具和浆料抛光过程中将其固定在位置的夹具中。

77. 发明申请

US20080230907A1 INTEGRATED CIRCUIT SYSTEM WITH CARBON ENHANCEMENT 审中-公开
标题翻译：具有碳增强的集成电路系统
公开(公告)号：US20080230907A1
公开(公告)日：2008-09-25
申请号：US11690080
申请日：2007-03-22
申请人： Wuping Liu , Kevin S. Petrarca , Johnny Widodo , Lawrence A. Clevenger , Wai-Kin Li
发明人： Wuping Liu , Kevin S. Petrarca , Johnny Widodo , Lawrence A. Clevenger , Wai-Kin Li
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76808 , H01L21/76825 , H01L21/76831 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; forming a via opening through the low-K dielectric layer to the interconnect layer; and forming a carbon implant region around the via opening, a trench opening, or a combination thereof, for protecting the low-K dielectric layer.
摘要翻译：提供一种集成电路硬掩模处理系统，包括提供具有集成电路的基板; 在所述集成电路上形成互连层; 在所述互连层上施加低K电介质层; 形成通过所述低K电介质层的通孔到所述互连层; 以及在通孔开口周围形成碳注入区域，沟槽开口或其组合，用于保护低K电介质层。

78. 发明授权

US06800503B2 MEMS encapsulated structure and method of making same 有权
标题翻译： MEMS封装结构及其制作方法
公开(公告)号：US06800503B2
公开(公告)日：2004-10-05
申请号：US10300520
申请日：2002-11-20
申请人： Joseph T. Kocis , James Tornello , Kevin S. Petrarca , Richard Volant , Seshadri Subbanna
发明人： Joseph T. Kocis , James Tornello , Kevin S. Petrarca , Richard Volant , Seshadri Subbanna
IPC分类号： H01L2100
CPC分类号： B81C1/00666 , B81B2201/014 , B81C2201/0167 , H01F2007/068 , H01H50/005
摘要： A method of fabricating an encapsulated micro electro-mechanical system (MEMS) and making of same that includes forming a dielectric layer, patterning an upper surface of the dielectric layer to form a trench, forming a release material within the trench, patterning an upper surface of the release material to form another trench, forming a first encapsulating layer that includes sidewalls within the another trench, forming a core layer within the first encapsulating layer, and forming a second encapsulating layer above the core layer, where the second encapsulating layer is connected to the sidewalls of the first encapsulating layer. Alternatively, the method includes forming a multilayer MEMS structure by photomasking processes to form a first metal layer, a second layer including a dielectric layer and a second metal layer, and a third metal layer. The core layer and the encapsulating layers are made of materials with complementary electrical, mechanical and/or magnetic properties.
摘要翻译：一种制造封装的微电子机械系统（MEMS）的方法及其制造方法，包括形成电介质层，图案化介电层的上表面以形成沟槽，在沟槽内形成释放材料，图案化上表面形成另一个沟槽，形成第一封装层，该第一封装层包括另一个沟槽内的侧壁，在第一封装层内形成核心层，以及在芯层上方形成第二封装层，其中第二封装层被连接到第一封装层的侧壁。或者，该方法包括通过光掩模工艺形成多层MEMS结构以形成第一金属层，第二层包括电介质层和第二金属层以及第三金属层。芯层和封装层由具有互补的电，机械和/或磁性的材料制成。

79. 发明授权

US06737725B2 Multilevel interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06737725B2
公开(公告)日：2004-05-18
申请号：US10144574
申请日：2002-05-13
申请人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
发明人： Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Satyanarayana Venkata Nitta , Kevin S. Petrarca , Sampath Purushothaman , Katherine Lynn Saenger , Stanley Joseph Whitehair
IPC分类号： H01L2900
CPC分类号： H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76835 , H01L21/76885
摘要： A method for forming a multilayer interconnect structure on a substrate that include interconnected conductive wiring and vias spaced apart by a combination of solid or gaseous dielectrics. The inventive method includes the steps of: (a) forming a first planar via plus line level pair embedded in a dielectric matrix formed from one or more solid dielectrics and comprising a via level dielectric and a line level dielectric on a substrate, wherein, at least one of said solid dielectrics is at least partially sacrificial; (b) etching back sacrificial portions of said at least partially sacrificial dielectrics are removed to leave cavities extending into and through said via level, while leaving, at least some of the original via level dielectric as a permanent dielectric under said lines; (c) partially filling or overfilling said cavities with a place-holder material which may or may not be sacrificial; (d) planarizing the structure by removing overfill of said place-holder material; (e) repeating, as necessary, steps (a)-(d); (f) forming a dielectric bridge layer over the planar structure; and (g) forming air gaps by at least partially extracting said place-holder material.
摘要翻译：一种在衬底上形成多层互连结构的方法，其包括互连的导电布线和通过固体或气体电介质的组合间隔开的通孔。本发明的方法包括以下步骤：（a）形成嵌入在由一个或多个固体电介质形成的电介质矩阵中并且包括通孔层电介质和衬底上的线路电介质的介电矩阵中的第一平面通孔加线电平对，其中，在至少一个所述固体电介质至少部分地是牺牲的; （b）蚀刻所述至少部分牺牲电介质的牺牲部分被去除以留下延伸进入并穿过所述通孔级的空腔，同时留下至少一些原始通孔级电介质作为所述线下的永久电介质; （c）用可能牺牲或可能不是牺牲的位置保持材料部分填充或过度填充所述空腔; （d）通过去除所述位置保持器材料的过量填充来平坦化结构; （e）必要时重复步骤（a） - （d）; （f）在所述平面结构上形成电介质桥接层; 和（g）通过至少部分地提取所述放置支架材料形成气隙。

80. 发明授权

US08614115B2 Photovoltaic solar cell device manufacture 失效
标题翻译：光伏太阳能电池器件制造
公开(公告)号：US08614115B2
公开(公告)日：2013-12-24
申请号：US12916236
申请日：2010-10-29
申请人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
发明人： Lawrence A. Clevenger , Harold J. Hovel , Rainer Klaus Krause , Kevin S. Petrarca , Gerd Pfeiffer , Kevin M. Prettyman , Carl Radens , Brian C. Sapp
IPC分类号： H01L21/00 , H01L31/18
CPC分类号： H01L31/022425 , H01L31/068 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： A method for manufacturing a photovoltaic solar cell device includes the following. A p-n junction having a first doping density is formed. Formation of the p-n junction is enhanced by introducing a second doping density to form high doped areas for a dual emitter application. The high doped areas are defined by a masking process integrated with the formation of the p-n junction, resulting in a mask pattern of the high doped areas. A metallization of the high doped areas occurs in accordance with the mask pattern of the high doped areas.
摘要翻译：光伏太阳能电池器件的制造方法包括以下。形成具有第一掺杂密度的p-n结。通过引入第二掺杂密度以形成用于双发射器应用的高掺杂区域来增强p-n结的形成。高掺杂区域由与p-n结的形成集成的掩模工艺限定，产生高掺杂区域的掩模图案。根据高掺杂区域的掩模图案发生高掺杂区域的金属化。

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