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71. 发明授权

US07489030B2 Stacked semiconductor device 有权
标题翻译：堆叠半导体器件
公开(公告)号：US07489030B2
公开(公告)日：2009-02-10
申请号：US11635500
申请日：2006-12-08
申请人： Kayoko Shibata , Hiroaki Ikeda , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
发明人： Kayoko Shibata , Hiroaki Ikeda , Yoshihiko Inoue , Hitoshi Miwa , Tatsuya Ijima
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/70 , H01L21/485 , H01L23/481 , H01L25/0657 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2224/16146 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06596 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599
摘要： As a defective contact recovery elements, a stacked semiconductor device include a parallel arrangement system in which signal paths are multiplexed, and a defective contact recovery circuit operable to switch a signal path into an auxiliary signal path. The parallel arrangement system is used in a case where the number of signals is small and a very high speed operation is required because of a serial data transfer. The defective contact recovery circuit is used in a case where the number of signals is large because of a parallel data transfer.
摘要翻译：作为有缺陷的接触恢复元件，堆叠半导体器件包括其中信号路径被复用的并行布置系统，以及可操作以将信号路径切换到辅助信号路径的缺陷接触恢复电路。在串行数据传输的情况下，使用并行布置系统，并且需要非常高速的操作。在由于并行数据传送而导致信号数量大的情况下使用有缺陷接触恢复电路。

72. 发明授权

US07450262B2 Form recognizing apparatus, form recognizing method, program and storage medium 失效
标题翻译：表格识别装置，表格识别方法，程序和存储介质
公开(公告)号：US07450262B2
公开(公告)日：2008-11-11
申请号：US10950212
申请日：2004-09-23
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G06K9/68
CPC分类号： G06Q10/107
摘要： A form recognizing apparatus, a form recognizing method and a form recognizing program for easily and precisely recognizing whether or not a form including multiple pages corresponds to any of multiple registered forms are disclosed. A form is registered. The registered form includes a feature amount and weight information of each page of the registered form. A page similarity value of each page of each of the registered forms is calculated by comparing a feature amount of each page of an input form image to be recognized and a feature amount of the corresponding page of the registered form. A form similarity value between the input form image to be recognized and each of the registered forms is calculated by weighting the page similarity values of the calculated pages by using weight information of the registered pages. A registered form corresponding to the form image to be recognized is determined.
摘要翻译：公开了一种形式识别装置，形式识别方法和形式识别程序，用于容易且精确地识别包括多个页面的表格是否对应于多个登记表格中的任何一个。注册表单。注册表格包括注册表单的每一页的特征量和权重信息。通过比较要识别的输入表单图像的每页的特征量和登记表单的相应页面的特征量来计算每个登记表单的每页的页面相似度值。通过使用登记页面的权重信息对所计算的页面的页面相似度值进行加权来计算要识别的输入表单图像与每个登记表单之间的表单相似度值。确定与要识别的表单图像相对应的登记表。

73. 发明申请

US20080226816A1 Method of manufacturing an electrode active material particle for a rechargeable battery 失效
标题翻译：制造可充电电池用电极活性物质粒子的方法
公开(公告)号：US20080226816A1
公开(公告)日：2008-09-18
申请号：US11979915
申请日：2007-11-09
申请人： Masahisa Fujimoto , Yasuyuki Kusumoto , Masahide Miyake , Hiroaki Ikeda , Shin Fujitani
发明人： Masahisa Fujimoto , Yasuyuki Kusumoto , Masahide Miyake , Hiroaki Ikeda , Shin Fujitani
IPC分类号： B05D3/00
CPC分类号： H01M4/134 , H01M4/364 , H01M4/38 , H01M4/386 , H01M4/387 , H01M4/626 , H01M10/052 , Y10T29/49115
摘要： A method of manufacturing an electrode active material particle for a rechargeable battery wherein a layer of an active material capable of being alloyed with Li is formed on a surface of a metal particle incapable of being alloyed with Li and then a heat treatment is conducted to diffuse the active material into the metal particle so that the resulting active material particle has a concentration profile in which a concentration of a metal element of the metal particle decreases from an interior toward the surface.
摘要翻译：一种制造可充电电池用电极活性物质粒子的方法，其特征在于，在不能与Li合金化的金属粒子的表面上形成能够与Li合金化的活性物质层，然后进行热处理活性物质进入金属颗粒，使得所得到的活性物质颗粒具有金属颗粒的金属元素的浓度从内部朝向表面降低的浓度分布。

74. 发明申请

US20080179728A1 Laminated memory 审中-公开
标题翻译：层压记忆
公开(公告)号：US20080179728A1
公开(公告)日：2008-07-31
申请号：US12010839
申请日：2008-01-30
申请人： Hiroaki Ikeda
发明人： Hiroaki Ikeda
IPC分类号： G11C8/00 , H01L23/02
CPC分类号： G11C5/02 , H01L21/6835 , H01L21/76898 , H01L23/544 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L27/0688 , H01L2221/6834 , H01L2221/68363 , H01L2223/54433 , H01L2223/5444 , H01L2224/81001 , H01L2224/81801 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107
摘要： A laminated memory is formed of first and second memory chips having different positions to dispose ID through electrodes for setting layer identification information of each layer. The memory chips are alternately stacked. By alternately stacking the layers, internal circuits for the layer identification information of each layer are connected in cascade. The cascade-connected internal circuits serve to identify respective layers of the first and the second memory chips. Identification of the respective layers makes it possible to selectively operate each memory chip.
摘要翻译：层叠存储器由具有不同位置的第一和第二存储器芯片形成，以通过用于设置每层的层标识信息的电极来设置ID。存储芯片交替堆叠。通过交替地堆叠层，用于每层的层识别信息的内部电路级联连接。级联连接的内部电路用于识别第一和第二存储器芯片的各个层。各层的识别使得可以选择性地操作每个存储芯片。

75. 发明申请

US20080133809A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20080133809A1
公开(公告)日：2008-06-05
申请号：US11987501
申请日：2007-11-30
申请人： Hideaki Saito , Hiroaki Ikeda
发明人： Hideaki Saito , Hiroaki Ikeda
IPC分类号： G06F13/42
CPC分类号： G06F13/1647 , G06F13/1684 , G11C7/10 , G11C7/1075 , G11C8/04
摘要： A semiconductor device, which allows a bank interleaving operation by issuing a write command and a read command to different banks while switching them without a waiting time to thereby prevent a drop in data transfer efficiency, is provided. The semiconductor device includes: a memory chip with banks each including at least one memory cell; a logic chip; and data buses, provided corresponding to the banks, for transmitting/receiving write data and read data between the banks and the logic chip. The logic chip includes: a writing data bus for transmitting write data to the memory chip via a data bus; a reading data bus for receiving read data from the memory chip via a data bus; and a switch for, corresponding to a write command or a read command to a bank, connecting the writing data bus or the reading data bus to a data bus connected to the bank.
摘要翻译：提供一种半导体器件，其通过在不间断的时间切换它们的同时向不同的库发出写入命令和读取命令来允许存储体交错操作，从而防止数据传送效率的下降。半导体器件包括：存储器芯片，每个存储器芯片包括至少一个存储单元; 一个逻辑芯片; 以及与银行对应的用于发送/接收写入数据和在存储体和逻辑芯片之间读取数据的数据总线。逻辑芯片包括：写入数据总线，用于经由数据总线将写入数据发送到存储器芯片; 读取数据总线，用于经由数据总线从存储器芯片接收读取数据; 以及用于对应于写入命令或对存储体的读取命令的开关，将写入数据总线或读取数据总线连接到连接到存储体的数据总线。

76. 发明授权

US07235330B1 Electrode for use in lithium battery and rechargeable lithium battery 失效
标题翻译：用于锂电池和可充电锂电池的电极
公开(公告)号：US07235330B1
公开(公告)日：2007-06-26
申请号：US10111070
申请日：2000-10-20
申请人： Masahisa Fujimoto , Shin Fujitani , Masaki Shima , Hiromasa Yagi , Hisaki Tarui , Hiroshi Kurokawa , Shigeki Matsuta , Yoichi Domoto , Yoshio Kato , Hiroshi Nakajima , Hiroaki Ikeda , Kenji Asaoka , Ryuji Ohshita
发明人： Masahisa Fujimoto , Shin Fujitani , Masaki Shima , Hiromasa Yagi , Hisaki Tarui , Hiroshi Kurokawa , Shigeki Matsuta , Yoichi Domoto , Yoshio Kato , Hiroshi Nakajima , Hiroaki Ikeda , Kenji Asaoka , Ryuji Ohshita
IPC分类号： H01M4/70 , H01M4/36
CPC分类号： H01M4/134 , H01M2/0207 , H01M4/04 , H01M4/131 , H01M4/1395 , H01M4/366 , H01M4/38 , H01M4/386 , H01M4/387 , H01M4/40 , H01M4/405 , H01M4/525 , H01M4/58 , H01M4/661 , H01M4/667 , H01M4/70 , H01M6/10 , H01M6/40 , H01M10/052 , H01M10/0587 , H01M10/44 , H01M2010/4292
摘要： An electrode for a lithium battery having a thin film composed of active material capable of lithium storage and release, e.g., a microcrystalline or amorphous silicon thin film, provided on a current collector, the electrode being characterized in that the current collector has a surface roughness Ra of 0.01 μm or greater.
摘要翻译：一种用于锂电池的电极，其具有由能够蓄积和释放的活性材料构成的薄膜，例如设置在集电器上的微晶或非晶硅薄膜，所述电极的特征在于，集电体具有表面粗糙度 Ra为0.01μm以上。

77. 发明申请

US20070117317A1 STACKED MEMORY 有权
标题翻译：堆叠内存
公开(公告)号：US20070117317A1
公开(公告)日：2007-05-24
申请号：US11560898
申请日：2006-11-17
申请人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
发明人： Hiroaki Ikeda , Kayoko Shibata , Junji Yamada
IPC分类号： H01L21/336 , H01L29/76
CPC分类号： G11C5/025
摘要： In a three-dimensional stacked memory having through electrodes, no optimal layer arrangement, bank arrangement, control methods have been established, and thus optimal methods are desired to be established. A stacked memory includes memory core layers, an interposer, and an IF chip. By stacking memory core layers having the same arrangement, it is possible to cope with both of no-oparity operation and parity operation. Further, bank designation irrespective of the number of stacks of the memory core layers can be achieved by assignment of a row address and a bank address. Further, the IF chip has refresh counters for performing a refresh control of the stacked memory. This arrangement provides a stacked memory including stacked memory core layers having through electrodes.
摘要翻译：在具有通过电极的三维堆叠存储器中，没有建立最优层布置，库布置，控制方法，因此希望建立最佳方法。堆叠存储器包括存储器核心层，插入器和IF芯片。通过堆叠具有相同布置的存储器核心层，可以处理无视操作和奇偶校验操作两者。此外，可以通过分配行地址和银行地址来实现与存储器核心层的堆栈数无关的库指定。此外，IF芯片具有用于执行堆叠存储器的刷新控制的刷新计数器。这种布置提供了包括具有通过电极的堆叠的存储器芯层的堆叠存储器。

78. 发明授权

US07119428B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07119428B2
公开(公告)日：2006-10-10
申请号：US11025634
申请日：2004-12-28
申请人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjo , Mitsuaki Katagiri , Yuji Watanabe
发明人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjo , Mitsuaki Katagiri , Yuji Watanabe
IPC分类号： H01L23/22 , H01L23/053 , H01L21/44
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73204 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
摘要翻译：提供一种能够在其操作期间降低温度升高的半导体器件。在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数的多个半导体元件。

79. 发明申请

US20060145301A1 Semiconductor chip and semiconductor device 审中-公开
标题翻译：半导体芯片和半导体器件
公开(公告)号：US20060145301A1
公开(公告)日：2006-07-06
申请号：US11326170
申请日：2006-01-05
申请人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
发明人： Hideaki Saito , Yasuhiko Hagihara , Hiroaki Ikeda
IPC分类号： H01L29/93
CPC分类号： H01L29/945 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.
摘要翻译：嵌入在半导体衬底中的导线被绝缘膜覆盖，并且偏置电压被施加到半导体衬底或线，以形成从绝缘膜的边缘延伸的耗尽层。或者，在半导体衬底内形成具有与半导体衬底不同的导电类型的半导体层以包围绝缘膜。

80. 发明授权

US06997108B2 Plate-making type printing press, multi-color printing press and plate-making type printing method 失效
公开(公告)号：US06997108B2
公开(公告)日：2006-02-14
申请号：US10222974
申请日：2002-08-19
申请人： Mitsuru Tabuchi , Hitoshi Hirose , Hiroya Nishii , Hajime Yagi , Masahiro Matsubara , Hiroaki Ikeda , Toshihiko Yamanaka
发明人： Mitsuru Tabuchi , Hitoshi Hirose , Hiroya Nishii , Hajime Yagi , Masahiro Matsubara , Hiroaki Ikeda , Toshihiko Yamanaka
IPC分类号： B41F7/02 , B41M5/00
CPC分类号： B41C1/1075
摘要： The plate-making printing press is constructed by installing a plate-making apparatus in a printing press that supplies ink and dampening water to a printing plate and performs printing on a medium. In order to realize a high-precision plate-making operation, the printing press is equipped with a target disposed on the printing cylinder and a sensor for detecting the target and provided on the writing device, and the zero point of the encoder is corrected. Furthermore, at the time of plate-making, the adjustment mechanism is operated so that the printing cylinder is returned to the position of the point of origin.

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