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71. 发明授权

US6096639A Method of forming a local interconnect by conductive layer patterning 失效
标题翻译：通过导电层图案形成局部互连的方法
公开(公告)号：US6096639A
公开(公告)日：2000-08-01
申请号：US056835
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76895
摘要： A local interconnect (LI) structure is formed by forming a silicide layer in selected regions of a semiconductor structure then depositing an essentially uniform layer of transition or refractory metal overlying the semiconductor structure. The metal local interconnect is deposited without forming in intermediate insulating layer between the silicide and metal layers to define contact openings or vias. In some embodiments, titanium a suitable metal for formation of the local interconnect. Suitable selected regions for silicide layer formation include, for example, silicided source/drain (S/D) regions and silicided gate contact regions. The silicided regions form uniform structures for electrical coupling to underlying doped regions that are parts of one or more semiconductor devices. In integrated circuits in which an etchstop layer is desired for the patterning of the metal film, a first optional insulating layer is deposited prior to deposition of the metal film. In one example, the insulating layer is a silicon dioxide (oxide) layer that is typically less than 10 nm in thickness.
摘要翻译：通过在半导体结构的选定区域中形成硅化物层然后沉积覆盖在半导体结构上的基本均匀的过渡或难熔金属层来形成局部互连（LI）结构。在硅化物和金属层之间的中间绝缘层中沉积金属局部互连以限定接触开口或通孔。在一些实施例中，钛是用于形成局部互连的合适金属。用于硅化物层形成的合适的选定区域包括例如硅化源极/漏极（S / D）区域和硅化物栅极接触区域。硅化区域形成均匀的结构，用于电耦合到作为一个或多个半导体器件的部分的下掺杂区域。在需要蚀刻阻挡层用于图案化金属膜的集成电路中，在沉积金属膜之前沉积第一可选绝缘层。在一个示例中，绝缘层是通常小于10nm厚度的二氧化硅（氧化物）层。

72. 发明授权

US6091149A Dissolvable dielectric method and structure 有权
标题翻译：溶解介电法和结构
公开(公告)号：US6091149A
公开(公告)日：2000-07-18
申请号：US251059
申请日：1999-02-18
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682
摘要： A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：提供一种制造工艺，其产生气隙电介质，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

73. 发明授权

US6087706A Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls 失效
标题翻译：紧凑的晶体管结构，具有相邻的沟槽隔离和源极/漏极区域，垂直注入沟槽壁
公开(公告)号：US6087706A
公开(公告)日：2000-07-11
申请号：US56834
申请日：1998-04-07
申请人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Robert Dawson , Mark I. Gardner , Frederick N. Hause , H. Jim Fulford, Jr. , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/265 , H01L21/762 , H01L21/8234 , H01L29/417 , H01L29/78 , H01L29/00 , H01L29/94
CPC分类号： H01L21/26586 , H01L21/76224 , H01L21/823418 , H01L21/823443 , H01L21/823475 , H01L21/823481 , H01L29/41766 , H01L29/66636 , H01L29/7833
摘要： A semiconductor integrated circuit with a transistor formed within an active area defined by side-walls of a shallow trench isolation region, and method of fabrication thereof, is described. A gate electrode is formed over a portion of the active area and LDD regions formed that are self-aligned to both the gate electrode and the trench side-walls. A dielectric spacer is formed adjacent the gate electrode and extending to the trench side-walls. In this manner, the spacers essentially cover the LDD regions. Source and drain regions are formed that are adjacent the trench side-walls wherein the spacer serves to protect at least a portion of the LDD regions to maintain a spacing of the S/D regions from the gate electrode edge. In this manner an advantageously lowered E.sub.M provided by LDD regions is maintained. In some embodiments of the present invention, S/D regions are formed by implantation through the trench side-walls.
摘要翻译：描述了一种形成在由浅沟槽隔离区域的侧壁限定的有源区域内的晶体管的半导体集成电路及其制造方法。在有源区域的一部分上形成栅电极，形成与栅极电极和沟槽侧壁自对准的LDD区域。形成在栅电极附近并延伸到沟槽侧壁的电介质垫片。以这种方式，间隔件基本上覆盖LDD区域。形成与沟槽侧壁相邻的源极区和漏极区，其中间隔物用于保护LDD区的至少一部分以保持S / D区与栅电极边缘的间隔。以这种方式，维持由LDD区域提供的有利的降低的EM。在本发明的一些实施例中，通过在沟槽侧壁上注入形成S / D区域。

74. 发明授权

US6049134A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳金属互连布局以实现全局平坦化的集成电路的掩模生成技术
公开(公告)号：US6049134A
公开(公告)日：2000-04-11
申请号：US15821
申请日：1998-01-29
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , H01L29/72 , H01L21/283
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

75. 发明授权

US6027859A Semiconductor substrate having extended scribe line test structure and method of fabrication thereof 失效
标题翻译：具有延长的划片线测试结构的半导体衬底及其制造方法
公开(公告)号：US6027859A
公开(公告)日：2000-02-22
申请号：US992234
申请日：1997-12-17
申请人： Robert Dawson , Mark W. Michael , Fred Hause
发明人： Robert Dawson , Mark W. Michael , Fred Hause
IPC分类号： G03F7/20
CPC分类号： G03F7/70633 , G03F7/70475
摘要： The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes forming a first test structure pattern over a first portion of the substrate and forming a second test structure pattern of the second portion of the substrate which partially overlaps the first portion of the substrate such that the first test structure pattern and the second test structure overlap. The first test structure pattern may be formed using, for example, reticle and a second test structure pattern may be formed using the same reticle. The first and second test structure patterns may, for example, be formed in a scribe line of the substrate.
摘要翻译：本发明通常提供具有扩展测试结构的半导体衬底和制造这种衬底的方法。根据本发明的一个实施例，在半导体衬底上形成扩展测试结构的方法包括在衬底的第一部分上形成第一测试结构图案，并形成衬底的第二部分的第二测试结构图案，部分地与衬底的第一部分重叠，使得第一测试结构图案和第二测试结构重叠。可以使用例如掩模版形成第一测试结构图案，并且可以使用相同的掩模版形成第二测试结构图案。第一和第二测试结构图案可以例如形成在基板的划线中。

76. 发明授权

US5998293A Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect 失效
标题翻译：具有气隙的集成电路的多层互连结构和分离互连级别的柱
公开(公告)号：US5998293A
公开(公告)日：1999-12-07
申请号：US67425
申请日：1998-04-28
申请人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
发明人： Robert Dawson , Mark W. Michael , William S. Brennan , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause
IPC分类号： H01L21/768 , H01L23/522 , H01L21/283
CPC分类号： H01L23/5226 , H01L21/7682 , H01L21/76885 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substrate. The pillars are spaced from each other by an air gap, such that each conductor within a level of interconnect is spaced by air from one another. Furthermore, each conductor within one level of interconnect is spaced by air from each conductor within another level of interconnect. Air gaps afford a smaller interlevel and intralevel capacitance within the multilevel interconnect structure, and a smaller parasitic capacitance value affords minimal propagation delay and cross-coupling noise of signals sent through the conductors. The air gaps are formed by dissolving a sacrificial dielectric, and the conductors are prevented from bending or warping in regions removed of sacrificial dielectric by employing anodization on not just the upper surfaces of each conductor, but the sidewalls as well. The upper and sidewall anodization provides a more rigid metal conductor structure than if merely the upper or sidewall surfaces were anodized. Accordingly, the pillars can be spaced further apart and yet provide all necessary support to the overlying conductors.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括跨越晶片彼此间隔开的柱。支柱放置在互连层之间或互连层和半导体衬底之间。支柱通过空气间隙彼此分开，使得互连级别内的每个导体彼此间隔着空气。此外，一个级别的互连中的每个导体在另一个互连级别内的每个导体间隔着空气。空气间隙在多电平互连结构内提供较小的层间和体积电容，并且较小的寄生电容值提供通过导体发送的信号的最小传播延迟和交叉耦合噪声。通过溶解牺牲电介质形成气隙，并且通过不仅在每个导体的上表面，而且侧壁上采用阳极氧化，防止导体在去除牺牲电介质的区域中弯曲或翘曲。上侧壁和侧壁阳极氧化提供了比仅仅将上表面或侧壁表面阳极氧化的更刚性的金属导体结构。因此，支柱可以进一步间隔开，并且向上覆的导体提供所有必要的支撑。

77. 发明授权

US5926717A Method of making an integrated circuit with oxidizable trench liner 失效
标题翻译：制造具有可氧化沟槽衬垫的集成电路的方法
公开(公告)号：US5926717A
公开(公告)日：1999-07-20
申请号：US763313
申请日：1996-12-10
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/762 , H01L21/76 , H01L21/62
CPC分类号： H01L21/76227
摘要： A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.
摘要翻译：一种用于将第一有源区与第二有源区隔离的方法，二者均配置在半导体衬底内。该方法包括在所述第一有源区和所述第二有源区之间的半导体衬底中形成沟槽。然后在所述沟槽上形成第一电介质层，并且在所述第一电介质层上沉积多晶硅层。然后将多晶硅层热氧化以形成第二介电层。优选地，第一电介质是厚度为40-500埃的热氧化物，其消耗小于200埃的所述第一有源区和所述第二活性区。多晶硅层优选为1000〜2000埃。

78. 发明授权

US5926713A Method for achieving global planarization by forming minimum mesas in large field areas 失效
标题翻译：通过在大场区域形成最小台面来实现全局平坦化的方法
公开(公告)号：US5926713A
公开(公告)日：1999-07-20
申请号：US923322
申请日：1997-09-04
申请人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/336 , H01L21/762
CPC分类号： H01L29/66712 , H01L21/31053 , H01L21/76229
摘要： An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space between silicon risers are ideally suited for optimal fill of a dielectric deposited across the semiconductor topography, i.e., across and between the silicon risers formed between active areas. The silicon risers, and optimally dimensioned trenches extending between the risers, enhance the planarity of the deposited dielectric. The deposited dielectric upper surface includes recesses of minimal elevational disparity, wherein the recesses are closely spaced in alignment directly above the trenches formed between silicon risers. The recesses can be readily removed by a chemical-mechanical polishing step with minimal deformity to the polishing pad, resulting in global planarization of the dielectric upper surface.
摘要翻译：提供隔离技术用于改善沟槽隔离区域相对于相邻硅台面的整体平面度。分离过程导致在宽隔离区域中形成间隔开的多个硅提升管。硅提升管之间的空间理想地适用于跨半导体形貌沉积的电介质的最佳填充，即在活性区域之间形成的硅提升板之间和之间。硅立管和在立管之间延伸的最佳尺寸的沟槽增强了沉积的电介质的平面性。沉积的电介质上表面包括具有最小高度差异的凹槽，其中凹槽在硅立管之间形成的沟槽的正上方紧密间隔开。可以通过化学机械抛光步骤容易地去除凹部，对抛光垫具有最小的变形，导致电介质上表面的全局平坦化。

79. 发明授权

US5924008A Integrated circuit having local interconnect for reducing signal cross coupled noise 失效
标题翻译：具有局部互连的集成电路，用于降低信号交叉耦合噪声
公开(公告)号：US5924008A
公开(公告)日：1999-07-13
申请号：US942248
申请日：1997-10-01
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.
摘要翻译：提供具有改进的互连结构的集成电路。互连结构包括总是保持在VDD或VSS（即接地）电平的功率耦合局部互连。局部互连在上覆互连的关键运行之下存在介电间隔距离。有源局部互连用于吸收临界导体的噪声瞬变，以确保连接到导体的电路不起作用。因此，局部互连沿着导体长度的大部分延伸，并且比其延伸的导体更宽或更窄。局部互连可以是多晶硅，掺杂多晶硅，多晶硅，难熔金属硅化物或多层难熔金属。

80. 发明授权

US5885887A Method of making an igfet with selectively doped multilevel polysilicon gate 失效
标题翻译：用选择性掺杂多电平多晶硅栅极制造igfet的方法
公开(公告)号：US5885887A
公开(公告)日：1999-03-23
申请号：US847752
申请日：1997-04-21
申请人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
发明人： Frederick N. Hause , Robert Dawson , H. Jim Fulford Jr. , Mark I. Gardner , Mark W. Michael , Bradley T. Moore , Derick J. Wristers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/423 , H01L21/38
CPC分类号： H01L29/6659 , H01L21/28114 , H01L21/823842 , H01L29/42376
摘要： A method of making an IGFET with a selectively doped multilevel polysilicon gate that includes upper and lower polysilicon gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a a lower polysilicon layer on the gate insulator, forming a first masking layer over the lower polysilicon layer, etching the lower polysilicon layer through openings in the first masking layer using the first masking layer as an etch mask for a portion of the lower polysilicon layer that forms the lower polysilicon gate level over the active region, removing the first masking layer, forming the upper polysilicon gate level on the lower polysilicon gate level after removing the first masking layer, introducing a dopant into the upper polysilicon gate level without introducing the dopant into the substrate, diffusing the dopant from the upper polysilicon gate level into the lower polysilicon gate level, and forming a source and drain in the active region. Advantageously, the lower polysilicon gate level has both an accurately defined length to provide the desired channel length and a well-controlled doping concentration to provide the desired threshold voltage.
摘要翻译：公开了一种制造具有选择性掺杂多电平多晶硅栅极的IGFET的方法，其包括上和下多晶硅栅极电平。该方法包括提供具有有源区的半导体衬底，在有源区上形成栅极绝缘体，在栅极绝缘体上形成下部多晶硅层，在下部多晶硅层上形成第一掩蔽层，通过下部多晶硅层的开口蚀刻下部多晶硅层所述第一掩模层使用所述第一掩模层作为用于在所述有源区上形成所述下多晶硅栅极电平的所述下多晶硅层的一部分的蚀刻掩模，去除所述第一掩模层，在所述下多晶硅栅极上形成所述上多晶硅栅极电平在去除第一掩模层之后，将掺杂剂引入上多晶硅栅极级，而不将掺杂剂引入衬底中，将掺杂剂从上多晶硅栅极级扩散到下多晶硅栅极电平，并在活性层中形成源极和漏极地区。有利地，下多晶硅栅极电平具有精确限定的长度以提供期望的沟道长度和良好控制的掺杂浓度以提供期望的阈值电压。

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