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    • 1. 发明授权
    • Photolithographic system including light filter that compensates for lens error
    • 光刻系统包括补偿透镜误差的滤光片
    • US06552776B1
    • 2003-04-22
    • US09183176
    • 1998-10-30
    • Derick J. WristersRobert DawsonH. Jim Fulford, Jr.Mark I. GardnerFrederick N. HauseBradley T. MooreMark W. Michael
    • Derick J. WristersRobert DawsonH. Jim Fulford, Jr.Mark I. GardnerFrederick N. HauseBradley T. MooreMark W. Michael
    • G03B2754
    • G03F7/70558G03F7/70191G03F7/706
    • A photolithographic system including a light filter that varies light intensity according to measured dimensional data that characterizes a lens error is disclosed. The light filter compensates for the lens error by reducing the light intensity of the image pattern as the lens error increases. In this manner, when the lens error causes focusing variations that result in enlarged portions of the image pattern, the light filter reduces the light intensity transmitted to the enlarged portions of the image pattern. This, in turn, reduces the rate in which regions of the photoresist layer beneath the enlarged portions of the image pattern are rendered soluble to a subsequent developer. As a result, after the photoresist layer is developed, linewidth variations that otherwise result from the lens error are reduced due to the light filter. Preferably, the light filter includes a light-absorbing film such as a semi-transparent layer such as calcium fluoride on a light-transmitting base such as a quartz plate, and the thickness of the light-absorbing film varies in accordance with the measured dimensional data to provide the desired variations in light intensity. The invention is particularly well-suited for patterning a photoresist layer that defines polysilicon gates of an integrated circuit device.
    • 公开了一种光刻系统,其包括根据测量的尺寸数据来表征透镜误差来改变光强度的滤光器。 光滤波器通过降低镜头误差增大时图像图案的光强度来补偿镜头误差。 以这种方式,当透镜错误导致导致图像图案的放大部分的聚焦变化时,光过滤器降低传输到图像图案的扩大部分的光强度。 这又降低了图像图案的放大部分之下的光致抗蚀剂层的区域变得可溶于后续显影剂的速率。 结果,在光致抗蚀剂层显影之后,由于滤光器而导致透镜误差导致的线宽变化会降低。 优选地,光滤波器包括诸如石英板等透光基底上的诸如氟化钙的半透明层的光吸收膜,并且光吸收膜的厚度根据测量的尺寸而变化 数据以提供所需的光强度变化。 本发明特别适用于图案化限定集成电路器件的多晶硅栅极的光致抗蚀剂层。
    • 2. 发明授权
    • Method of making NMOS and PMOS devices with reduced masking steps
    • 制造具有减少掩蔽步骤的NMOS和PMOS器件的方法
    • US6060345A
    • 2000-05-09
    • US844924
    • 1997-04-21
    • Frederick N. HauseRobert DawsonH. Jim Fulford, Jr.Mark I. GardnerMark W. MichaelBradley T. MooreDerick J. Wristers
    • Frederick N. HauseRobert DawsonH. Jim Fulford, Jr.Mark I. GardnerMark W. MichaelBradley T. MooreDerick J. Wristers
    • H01L21/8238H01L27/092
    • H01L21/823814
    • A method of making NMOS and PMOS devices with reduced masking steps is disclosed. The method includes providing a semiconductor substrate with a first active region of first conductivity type and a second active region of second conductivity type, forming a gate material over the first and second active regions, forming a first masking layer over the gate material, etching the gate material using the first masking layer as an etch mask to form a first gate over the first active region and a second gate over the second active region, implanting a dopant of second conductivity type into the first and second active regions using the first masking layer as an implant mask, forming a second masking layer that covers the first active region and includes an opening above the second active region, and implanting a dopant of first conductivity type into the second active region using the first and second masking layers as an implant mask. Advantageously, the dopant of first conductivity type counterdopes the dopant of second conductivity type in the second active region, thereby providing source and drain regions of second conductivity type in the first active region and source and drain regions of first conductivity type in the second active region with a single masking step and without subjecting either gate to dopants of first and second conductivity type.
    • 公开了一种制造具有减小的掩蔽步骤的NMOS和PMOS器件的方法。 该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底,在第一和第二有源区上形成栅极材料,在栅极材料上形成第一掩模层, 栅极材料,使用第一掩模层作为蚀刻掩模,以在第一有源区上形成第一栅极,在第二有源区上形成第二栅极,使用第一掩模层将第二导电类型的掺杂剂注入到第一和第二有源区中 作为注入掩模,形成覆盖第一有源区并且包括在第二有源区上方的开口的第二掩模层,以及使用第一和第二掩模层作为注入掩模将第一导电类型的掺杂剂注入到第二有源区中 。 有利地,第一导电类型的掺杂剂在第二有源区域中抵消第二导电类型的掺杂剂,从而在第一有源区域中提供第二导电类型的源极和漏极区域,并且在第二有源区域中提供第一导电类型的源极和漏极区域 具有单个掩蔽步骤,并且不对任一个栅极施加第一和第二导电类型的掺杂剂。
    • 3. 发明授权
    • Trench transistor with metal spacers
    • 沟槽晶体管与金属间隔
    • US5962894A
    • 1999-10-05
    • US30052
    • 1998-02-24
    • Mark I. GardnerRobert DawsonH. Jim Fulford, Jr.Frederick N. HauseMark W. MichaelBradley T. MooreDerick J. Wristers
    • Mark I. GardnerRobert DawsonH. Jim Fulford, Jr.Frederick N. HauseMark W. MichaelBradley T. MooreDerick J. Wristers
    • H01L21/336H01L29/417H01L29/423H01L29/76H01L31/062
    • H01L29/41775H01L29/66621H01L29/78
    • An IGFET with a gate electrode and metal spacers in a trench is disclosed. The IGFET includes a trench with opposing sidewalls and a bottom surface in a semiconductor substrate, metal spacers adjacent to the sidewalls and the bottom surface, a gate insulator on the bottom surface between the metal spacers, protective insulators on the metal spacers, a gate electrode on the gate insulator and protective insulators, and a source and drain adjacent to the bottom surface. A method of forming the IGFET includes implanting a doped layer into the substrate, etching completely through the doped layer and partially through the substrate to form the trench and split the doped layer into source and drain regions, applying a high-temperature anneal to diffuse the source and drain regions beneath the bottom surface, depositing a blanket layer of conductive metal over the substrate and applying an anisotropic etch to form the metal spacers, depositing a continuous insulative layer over the substrate to provide the gate insulator and the protective insulators, depositing a blanket layer of gate electrode material over the substrate, and polishing the gate electrode material so that the gate electrode is substantially aligned with a top surface of the substrate. Advantageously, the channel length is significantly smaller than the trench length, and the metal spacers reduce the parasitic resistance of lightly doped source and drain regions.
    • 公开了具有沟槽中的栅电极和金属间隔物的IGFET。 IGFET包括具有相对的侧壁和半导体衬底中的底表面的沟槽,与侧壁和底表面相邻的金属间隔物,位于金属间隔物之间​​的底表面上的栅极绝缘体,金属间隔物上的保护绝缘体,栅电极 在栅极绝缘体和保护绝缘体上,以及与底表面相邻的源极和漏极。 形成IGFET的方法包括将掺杂层注入到衬底中,完全通过掺杂层蚀刻并部分地穿过衬底以形成沟槽并将掺杂层分裂成源极和漏极区域,施加高温退火以扩散 在底表面下方的源极和漏极区域,在衬底上沉积导电金属的覆盖层,并施加各向异性蚀刻以形成金属间隔物,在衬底上沉积连续的绝缘层以提供栅极绝缘体和保护绝缘体, 覆盖衬底上的栅电极材料层,并且对栅电极材料进行抛光,使得栅电极基本上与衬底的顶表面对准。 有利地,沟道长度显着小于沟槽长度,并且金属间隔物减少了轻掺杂源极和漏极区域的寄生电阻。
    • 4. 发明授权
    • Method of making an IGFET with a multilevel gate
    • 制造具有多级门的IGFET的方法
    • US5930634A
    • 1999-07-27
    • US844927
    • 1997-04-21
    • Frederick N. HauseRobert DawsonH. Jim Fulford, Jr.Mark I. GardnerMark W. MichaelBradley T. MooreDerick J. Wristers
    • Frederick N. HauseRobert DawsonH. Jim Fulford, Jr.Mark I. GardnerMark W. MichaelBradley T. MooreDerick J. Wristers
    • H01L21/28H01L21/336H01L29/423H01L29/49H01L29/78
    • H01L29/66575H01L21/28035H01L21/28052H01L29/42376H01L29/4925H01L29/6659H01L29/7833
    • A method of making an IGFET with a multilevel gate that includes upper and lower gate levels is disclosed. The method includes providing a semiconductor substrate with an active region, forming a gate insulator on the active region, forming a first gate material with a thickness of at most 1000 angstroms on the gate inslator and over the active region, forming a first photoresist layer over the first gate material, irradiating the first photoresist layer with a first image pattern and removing irradiated portions of the first photoresist layer to provide openings above the active region, etching the first gate material through the openings in the first photoresist layer using the first photoresist layer as an etch mask for a portion of the first gate material that forms a lower gate level, removing the first photoresist layer, forming an upper gate level on the lower gate level after removing the first photoresist layer, and forming a source and drain in the active region. Advantageously, the first photoresist layer can be ultra-thin to enhance the accuracy in which the image pattern is replicated, thereby reducing variations in channel length and device performance.
    • 公开了一种制造具有包括上下栅极电平的多电平栅极的IGFET的方法。 该方法包括提供具有有源区的半导体衬底,在有源区上形成栅极绝缘体,在栅极绝缘体上并在有源区上形成厚度至多为1000埃的第一栅极材料,形成第一光致抗蚀剂层 第一栅极材料,用第一图案图案照射第一光致抗蚀剂层,并去除第一光致抗蚀剂层的照射部分以在有源区上方提供开口,使用第一光致抗蚀剂层蚀刻通过第一光致抗蚀剂层中的开口的第一栅极材料 作为用于形成下栅极电平的第一栅极材料的一部分的蚀刻掩模,去除第一光致抗蚀剂层,在去除第一光致抗蚀剂层之后在下栅极电平上形成上栅极电平,并在其中形成源极和漏极 活跃区域。 有利地,第一光致抗蚀剂层可以是超薄的,以提高复制图像图案的精度,从而减少通道长度和器件性能的变化。
    • 7. 发明授权
    • Method and apparatus for in situ anneal during ion implant
    • 离子注入过程中原位退火的方法和装置
    • US6111260A
    • 2000-08-29
    • US872258
    • 1997-06-10
    • Robert DawsonH. Jim Fulford, Jr.Mark I. GardnerFrederick N. HauseMark W. MichaelBradley T. MooreDerick J. Wristers
    • Robert DawsonH. Jim Fulford, Jr.Mark I. GardnerFrederick N. HauseMark W. MichaelBradley T. MooreDerick J. Wristers
    • H01J37/317
    • H01J37/3171H01J2237/316
    • During a semiconductor substrate ion implant process thermal energy is supplied to raise the temperature of the semiconductor wafer. The increased temperature of the semiconductor wafer during implantation acts to anneal the implanted impurities or dopants in the wafer, reducing impurity diffusion and reducing the number of fabrication process steps. An ion implant device includes an end station that is adapted for application and control of thermal energy to the end station for raising the temperature of a semiconductor substrate wafer during implantation. The adapted end station includes a heating element for heating the semiconductor substrate wafer, a thermocouple for sensing the temperature of the semiconductor substrate wafer, and a controller for monitoring the sensed temperature and controlling the thermal energy applied to the semiconductor substrate wafer by the heating element. An ion implant device including a system for applying and controlling thermal energy applied to a semiconductor substrate wafer during ion implantation raises the temperature of the wafer to a temperature that is sufficient to activate impurities within the semiconductor substrate wafer when an ion beam is implanting ions to the wafer, but the temperature is insufficient to activate impurities when the ion beam is inactive.
    • 在半导体衬底离子注入过程中,提供热能以提高半导体晶片的温度。 在注入期间半导体晶片的温度升高期间用于退火晶片中注入的杂质或掺杂剂,减少杂质扩散并减少制造工艺步骤的数量。 离子注入装置包括终端站,其适于向端站施加和控制热能,以在植入期间提高半导体衬底晶片的温度。 适用的端站包括用于加热半导体衬底晶片的加热元件,用于感测半导体衬底晶片的温度的热电偶,以及用于监测感测温度并通过加热元件控制施加到半导体衬底晶片的热能的控制器 。 包括用于在离子注入期间施加和控制施加到半导体衬底晶片的热能的系统的离子注入装置将晶片的温度升高到当离子束注入离子时足以激活半导体衬底晶片内的杂质的温度 晶片,但当离子束无效时,温度不足以激活杂质。