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71. 发明授权

US08865592B2 Silicided semiconductor structure and method of forming the same 有权
标题翻译：硅化半导体结构及其形成方法
公开(公告)号：US08865592B2
公开(公告)日：2014-10-21
申请号：US12364804
申请日：2009-02-03
申请人： Jiang Yan , Henning Haffner , Frank Huebinger , SunOo Kim , Richard Lindsay , Klaus Schruefer
发明人： Jiang Yan , Henning Haffner , Frank Huebinger , SunOo Kim , Richard Lindsay , Klaus Schruefer
IPC分类号： H01L21/44 , H01L23/525 , H01L21/28 , H01L29/49
CPC分类号： H01L27/0617 , H01L21/28088 , H01L23/5256 , H01L29/0653 , H01L29/4958 , H01L29/4966 , H01L2924/0002 , H01L2924/00
摘要： A preferred embodiment includes a method of manufacturing a fuse element that includes forming a polysilicon layer over a semiconductor structure, doping the polysilicon layer with carbon or nitrogen, depositing a metal over the polysilicon layer; and annealing the metal and polysilicon layer to form a silicide in an upper portion of the polysilicon layer.
摘要翻译：优选实施例包括制造熔丝元件的方法，该方法包括在半导体结构上形成多晶硅层，用碳或氮掺杂多晶硅层，在多晶硅层上沉积金属; 以及退火所述金属和多晶硅层以在所述多晶硅层的上部形成硅化物。

72. 发明申请

US20140015068A1 Gate Structure, Semiconductor Device and Methods for Forming the Same 审中-公开
标题翻译：门结构，半导体器件及其形成方法
公开(公告)号：US20140015068A1
公开(公告)日：2014-01-16
申请号：US13699731
申请日：2012-07-24
申请人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
发明人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/495 , H01L21/28008 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer.
摘要翻译：本公开涉及一种栅极结构，半导体器件及其形成方法。本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供基板; 在衬底上形成界面层; 在界面层上形成栅介电层; 在所述栅极电介质层上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成氧清除元件盖层; 执行金属后退火; 进行蚀刻，直到蚀刻停止层露出为止; 在所述蚀刻停止层上形成功函数调整层; 以及在所述功函数调整层上形成栅极层。

73. 发明申请

US20140015063A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 有权
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015063A1
公开(公告)日：2014-01-16
申请号：US13699734
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

74. 发明申请

US20140015062A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 审中-公开
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015062A1
公开(公告)日：2014-01-16
申请号：US13699732
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供衬底，其中衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且栅极沟槽在底部设置有栅极电介质层; 在所述衬底的表面上形成栅介电覆盖层; 在所述栅介质顶盖层上形成氧清除元件层; 在除氧元件层上形成蚀刻停止层; 在所述蚀刻停止层上形成功函数调整层; 执行金属层沉积和退火工艺以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

75. 发明授权

US08541296B2 Method of manufacturing dummy gates in gate last process 有权
标题翻译：门最后工序中制造虚拟门的方法
公开(公告)号：US08541296B2
公开(公告)日：2013-09-24
申请号：US13510730
申请日：2011-11-30
申请人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Jiang Yan , Junfeng Li , Yihong Lu , Dapeng Chen
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/31111 , H01L21/32139 , H01L29/51
摘要： The present invention provides a method of manufacturing a dummy gate in a gate last process, which comprises the steps of forming a dummy gate material layer and a hard mask material layer sequentially on a substrate; etching the hard mask material layer to form a top-wide-bottom-narrow hard mask pattern; dry etching the dummy gate material layer using the hard mask pattern as a mask to form a top-wide-bottom-narrow dummy gate. According to the dummy gate manufacturing method of the present invention, instead of vertical dummy gates used conventionally, top-wide-bottom-narrow trapezoidal dummy gates are formed, and after removing the dummy gates, trapezoidal trenches can be formed. It facilitates the subsequent filling of the high-k or metal gate material and enlarges the window for the filling process; as a result, the device reliability will be improved.
摘要翻译：本发明提供一种在栅极最后工艺中制造虚拟栅极的方法，其包括以下步骤：在衬底上依次形成虚拟栅极材料层和硬掩模材料层; 蚀刻硬掩模材料层以形成顶部宽底部窄的硬掩模图案; 使用硬掩模图案作为掩模对伪栅极材料层进行干蚀刻以形成顶部 - 宽度 - 底部 - 窄度的虚拟栅极。根据本发明的虚拟栅极制造方法，代替常规使用的垂直虚拟栅极，形成顶部 - 宽度 - 底部 - 窄 - 窄的梯形伪栅极，并且在去除伪栅极之后，可以形成梯形沟槽。它有利于随后填充高k或金属栅极材料，并扩大了填充过程的窗口; 结果，设备的可靠性将得到提高。

76. 发明授权

US08501500B2 Method for monitoring the removal of polysilicon pseudo gates 有权
标题翻译：监测多晶硅伪栅极去除的方法
公开(公告)号：US08501500B2
公开(公告)日：2013-08-06
申请号：US13499288
申请日：2011-11-29
申请人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
发明人： Tao Yang , Chao Zhao , Junfeng Li , Jiang Yan , Dapeng Chen
IPC分类号： H01L21/66
CPC分类号： H01L22/12 , H01L29/66545
摘要： The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer.
摘要翻译：本发明公开了一种用于监测多晶硅虚拟栅极去除的方法，包括以下步骤：在晶片的表面上形成多晶硅虚拟栅极结构; 确定晶片的测量目标和质量的误差范围; 以及通过质量测量工具在多晶硅虚拟栅极去除之后测量晶片的质量，以确定多晶硅虚拟栅极是否被完全去除。根据本发明的测量方法，可以快速且准确地测量全晶片而不需要特定的测试结构，以有效地监测和确定多晶硅虚拟栅极是否被彻底去除，同时所述测量方法直接，快速地给出反馈，准确地不会对晶片造成任何损坏。

77. 发明授权

US08319285B2 Silicon-on-insulator chip having multiple crystal orientations 有权
标题翻译：具有多个晶体取向的绝缘体上硅芯片
公开(公告)号：US08319285B2
公开(公告)日：2012-11-27
申请号：US11315069
申请日：2005-12-22
申请人： Armin Tilke , Jiang Yan , Matthias Hierlemann
发明人： Armin Tilke , Jiang Yan , Matthias Hierlemann
IPC分类号： H01L29/04
CPC分类号： H01L29/045 , H01L21/265 , H01L21/76 , H01L21/76251 , H01L21/84 , H01L23/5256 , H01L27/1203 , H01L29/7842 , H01L2924/0002 , H01L2924/00
摘要： A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.
摘要翻译：公开了具有多个晶体取向的绝缘体上硅器件。在一个实施例中，绝缘体上硅器件包括衬底层，设置在衬底层上的绝缘层，第一硅层和应变硅层。第一硅层具有第一晶体取向并且设置在绝缘层的一部分上，并且应变硅层设置在绝缘层的另一部分上并且具有不同于第一晶体取向的晶体取向。

78. 发明申请

US20120196432A1 Method for Manufacturing Contact Holes in CMOS Device Using Gate-Last Process 有权
标题翻译：使用栅极最后工艺在CMOS器件中制造接触孔的方法
公开(公告)号：US20120196432A1
公开(公告)日：2012-08-02
申请号：US13141982
申请日：2011-02-21
申请人： Jiang Yan
发明人： Jiang Yan
IPC分类号： H01L21/28
CPC分类号： H01L21/823871 , H01L21/823814 , H01L23/485 , H01L29/495 , H01L29/4966 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing contact holes in a CMOS device by using a gate-last process, comprising: forming high-K dielectrics/metal gates (HKMG) of a first type MOS; forming and metalizing lower contact holes of the source/drain of a first type MOS and a second type MOS as well as forming HKMG of a second type MOS simultaneously, wherein the lower contact holes of the source/drain are filled with the same material as that used by the metal gate of the second type MOS; forming and metalizing contact holes of metal gates of a first type MOS and a second type MOS as well as upper contact holes of the source/drain, wherein the upper contact holes of the source/drain are aligned with the lower contact holes of the source/drain. The method reduces the difficulty of contact hole etching and metal deposition, simplifies the process steps, and increases the reliability of the device.
摘要翻译：本发明提供了一种通过使用栅极最后工艺在CMOS器件中制造接触孔的方法，包括：形成第一类型MOS的高K电介质/金属栅极（HKMG）; 形成和金属化第一类型MOS和第二类型MOS的源极/漏极的下部接触孔，同时形成第二类型的MOS的HKMG，其中源极/漏极的下部接触孔用与由第二类MOS的金属栅使用; 形成和金属化第一类型MOS和第二类型MOS的金属栅极的接触孔以及源极/漏极的上部接触孔，其中源极/漏极的上接触孔与源极的下接触孔对准 /排水。该方法降低了接触孔蚀刻和金属沉积的难度，简化了工艺步骤，并提高了器件的可靠性。

79. 发明授权

US08173502B2 Formation of active area using semiconductor growth process without STI integration 有权
标题翻译：使用半导体生长过程形成活性区，无需STI整合
公开(公告)号：US08173502B2
公开(公告)日：2012-05-08
申请号：US13156944
申请日：2011-06-09
申请人： Jiang Yan , Danny Pak-Chum Shum
发明人： Jiang Yan , Danny Pak-Chum Shum
IPC分类号： H01L21/336 , H01L21/331 , H01L21/02
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.
摘要翻译：可以不使用STI工艺来形成半导体器件。在半导体本体上形成绝缘层。绝缘层的一部分被去除以暴露半导体本体，例如露出裸硅。半导体材料，例如硅，生长在暴露的半导体本体上。然后可以在生长的半导体材料中形成诸如晶体管的器件。

80. 发明申请

US20110237035A1 Formation of Active Area Using Semiconductor Growth Process without STI Integration 有权
标题翻译：使用无STI集成的半导体生长工艺形成有源区
公开(公告)号：US20110237035A1
公开(公告)日：2011-09-29
申请号：US13156944
申请日：2011-06-09
申请人： Jiang Yan , Danny Pak-Chum Shum
发明人： Jiang Yan , Danny Pak-Chum Shum
IPC分类号： H01L21/336 , H01L21/331 , H01L21/02
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/02639
摘要： A semiconductor device can be formed without use of an STI process. An insulating layer is formed over a semiconductor body. Portions of the insulating layer are removed to expose the semiconductor body, e.g., to expose bare silicon. A semiconductor material, e.g., silicon, is grown over the exposed semiconductor body. A device, such as a transistor, can then be formed in the grown semiconductor material.
摘要翻译：可以不使用STI工艺来形成半导体器件。在半导体本体上形成绝缘层。绝缘层的一部分被去除以暴露半导体本体，例如露出裸硅。半导体材料，例如硅，生长在暴露的半导体本体上。然后可以在生长的半导体材料中形成诸如晶体管的器件。

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