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1. 发明申请

US20140015063A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 有权
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015063A1
公开(公告)日：2014-01-16
申请号：US13699734
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

2. 发明申请

US20140015062A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 审中-公开
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015062A1
公开(公告)日：2014-01-16
申请号：US13699732
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供衬底，其中衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且栅极沟槽在底部设置有栅极电介质层; 在所述衬底的表面上形成栅介电覆盖层; 在所述栅介质顶盖层上形成氧清除元件层; 在除氧元件层上形成蚀刻停止层; 在所述蚀刻停止层上形成功函数调整层; 执行金属层沉积和退火工艺以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

3. 发明授权

US08921171B2 Method for forming gate structure, method for forming semiconductor device, and semiconductor device 有权
标题翻译：用于形成栅极结构的方法，用于形成半导体器件的方法和半导体器件
公开(公告)号：US08921171B2
公开(公告)日：2014-12-30
申请号：US13699734
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

4. 发明申请

US20140015068A1 Gate Structure, Semiconductor Device and Methods for Forming the Same 审中-公开
标题翻译：门结构，半导体器件及其形成方法
公开(公告)号：US20140015068A1
公开(公告)日：2014-01-16
申请号：US13699731
申请日：2012-07-24
申请人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
发明人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/495 , H01L21/28008 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer.
摘要翻译：本公开涉及一种栅极结构，半导体器件及其形成方法。本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供基板; 在衬底上形成界面层; 在界面层上形成栅介电层; 在所述栅极电介质层上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成氧清除元件盖层; 执行金属后退火; 进行蚀刻，直到蚀刻停止层露出为止; 在所述蚀刻停止层上形成功函数调整层; 以及在所述功函数调整层上形成栅极层。

5. 发明授权

US08507991B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08507991B2
公开(公告)日：2013-08-13
申请号：US13517893
申请日：2012-06-14
申请人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
发明人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
IPC分类号： H01L29/76 , H01L29/94 , H01L27/108 , H01L31/119 , H01L31/062
CPC分类号： H01L21/823857 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.
摘要翻译：提供半导体器件。通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单原子结构的超薄高k电介质材料形成包含衬底元件的多组分高k界面层，并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。

6. 发明申请

US20120261761A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120261761A1
公开(公告)日：2012-10-18
申请号：US13517893
申请日：2012-06-14
申请人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
发明人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device is provided. A multi-component high-k interface layer containing elements of the substrate is formed from an ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment.
摘要翻译：提供半导体器件。通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单原子结构的超薄高k电介质材料形成包含衬底元件的多组分高k界面层，并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。

7. 发明授权

US08222099B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08222099B2
公开(公告)日：2012-07-17
申请号：US13063564
申请日：2010-06-24
申请人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
发明人： Wenwu Wang , Kai Han , Shijie Chen , Xiaolei Wang , Dapeng Chen
IPC分类号： H01L27/088
CPC分类号： H01L21/823857 , H01L29/66545 , Y10S438/926
摘要： A semiconductor device and a method of manufacturing the same are provided. A multi-component high-k interface layer containing elements of the substrate is formed from a ultra-thin high-k dielectric material in a single-layer structure of atoms by rapid annealing in the manufacturing of a CMOS transistor by the replacement gate process, and a high-k gate dielectric layer with a higher dielectric constant and a metal gate layer are formed thereon. The EOT of the device is effectively decreased, and the diffusion of atoms in the high-k gate dielectric layer from an upper level thereof is effectively prevented by the optimized high-k interface layer at high-temperature treatment. Thus, the present invention may also avoid the growth of the interface layers and the degradation of carrier mobility. Furthermore, the present invention may further alleviate the problem of high interface state and interface roughness caused by direct contact of the high-k gate dielectric layer with high dielectric constant and the substrate, and thus the overall performance of the device is effectively enhanced.
摘要翻译：提供半导体器件及其制造方法。通过在通过替换栅极工艺制造CMOS晶体管中的快速退火，通过单层原子结构的超薄高k介电材料形成包含衬底元件的多组分高k界面层，并且在其上形成具有较高介电常数的高k栅极电介质层和金属栅极层。有效地减少器件的EOT，并且通过在高温处理下的优化的高k界面层有效地防止了高k栅介质层中的原子从其上层的扩散。因此，本发明还可以避免界面层的生长和载流子迁移率的劣化。此外，本发明还可以进一步减轻高介电常数和高介电常数直接接触引起的高界面态和界面粗糙度问题，从而有效提高器件的整体性能。

8. 发明授权

US08563415B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08563415B2
公开(公告)日：2013-10-22
申请号：US13061879
申请日：2010-06-24
申请人： Wenwu Wang , Shijie Chen , Xiaolei Wang , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Shijie Chen , Xiaolei Wang , Kai Han , Dapeng Chen
IPC分类号： H01L21/3205 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/28176 , H01L29/4916 , H01L29/4966 , H01L29/4975 , H01L29/513 , H01L29/517
摘要： The present invention relates to a method of manufacturing a semiconductor device. After depositing the metal gate electrode material, a layer of oxygen molecule catalyzing layer having a catalyzing function to the oxygen molecules is deposited, and afterwards, a low-temperature PMA annealing process is used to decompose the oxygen molecules in the annealing atmosphere into more active oxygen atoms. These oxygen atoms are diffused into the high-k gate dielectric film through the metal gate to supplement the oxygen vacancies in the high-k film, in order to alleviate oxygen vacancies in the high-k film and improve the quality of the high-k film. According to the present invention, the oxygen vacancies and defects of high-k gate dielectric film will be alleviated, and further, growth of SiOx interface layer having a low dielectric constant caused by the traditional PDA high temperature process may be prevented. Thereby, the EOT of the entire gate dielectric layer may be effectively controlled, and the MOS device may be continuously scaled. Meanwhile, the present invention further provides a semiconductor device obtained according to the above-mentioned method.
摘要翻译：本发明涉及半导体器件的制造方法。沉积金属栅电极材料后，沉积具有对氧分子具有催化功能的氧分子催化层，然后使用低温PMA退火工艺将退火气氛中的氧分子分解为更有活性的氧原子。这些氧原子通过金属栅极扩散到高k栅极电介质膜中，以补充高k膜中的氧空位，以便减轻高k膜中的氧空位并提高高k的质量电影。根据本发明，可以减轻高k栅极电介质膜的氧空位和缺陷，并且可以防止由传统的PDA高温过程引起的具有低介电常数的SiO x界面层的生长。由此，可以有效地控制整个栅介质层的EOT，并且可以连续地缩放MOS器件。同时，本发明还提供了根据上述方法获得的半导体器件。

9. 发明授权

US08633098B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08633098B2
公开(公告)日：2014-01-21
申请号：US13061774
申请日：2010-09-28
申请人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
发明人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/4908 , H01L21/28176 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.
摘要翻译：本发明涉及半导体制造领域。本发明提供一种制造半导体器件的方法，其包括：提供半导体衬底; 在基板上形成界面层，栅极电介质层和栅电极; 在栅电极上形成金属氧吸收层; 对半导体器件进行热退火处理，使得金属氧吸收层吸收界面层中的氧，并且界面层的厚度减小。通过本发明，一方面可以减小界面层的厚度，另一方面，通过金属氧化物吸收层中的金属氧化物吸收层中的金属扩散到栅电极和/或栅电介质层退火工艺，进一步实现了调节有效功函数和控制阈值电压的效果。

10. 发明申请

US20120021596A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120021596A1
公开(公告)日：2012-01-26
申请号：US13061774
申请日：2010-09-28
申请人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
发明人： Kai Han , Wenwu Wang , Xiaolei Wang , Shijie Chen , Dapeng Chen
IPC分类号： H01L21/28
CPC分类号： H01L29/4908 , H01L21/28176 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present invention relates to the field of semiconductor manufacturing. The present invention provides a method of manufacturing a semiconductor device, which comprises: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer and a gate electrode on the substrate; forming a metal oxygen absorption layer on the gate electrode; performing a thermal annealing process on the semiconductor device so that the metal oxygen absorption layer absorbs oxygen in the interface layer and the thickness of the interface layer is reduced. By means of the present invention, the thickness of the interface layer can be reduced on one hand, and on the other hand the metal in the metal oxygen absorption layer is made to diffuse into the gate electrode and/or the gate dielectric layer through the annealing process, which further achieves the effects of adjusting the effective work function and controlling the threshold voltage.
摘要翻译：本发明涉及半导体制造领域。本发明提供一种制造半导体器件的方法，其包括：提供半导体衬底; 在基板上形成界面层，栅极电介质层和栅电极; 在栅电极上形成金属氧吸收层; 对半导体器件进行热退火处理，使得金属氧吸收层吸收界面层中的氧，并且界面层的厚度减小。通过本发明，一方面可以减小界面层的厚度，另一方面，通过金属氧化物吸收层中的金属氧化物吸收层中的金属扩散到栅电极和/或栅电介质层退火工艺，进一步实现了调节有效功函数和控制阈值电压的效果。

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