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71. 发明授权

US08080838B2 Contact scheme for FINFET structures with multiple FINs 有权
标题翻译：具有多个FIN的FINFET结构的接触方案
公开(公告)号：US08080838B2
公开(公告)日：2011-12-20
申请号：US12434233
申请日：2009-05-01
申请人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
发明人： Leland Chang , Wilfried E. Haensch , Meikei Ieong , Ghavam Shahidi , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66628 , H01L29/66795
摘要： A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.
摘要翻译：提供了一种具有融合在一起而没有源极/漏极接触焊盘或局部互连的多个FIN的具有FINFET的结构。该结构包括在衬底的表面上方延伸的多个半导电体（即，FIN）。常见的图案化栅极堆叠围绕多个半导体本体，并且含氮化物的间隔物位于公共图案化栅叠层的侧壁上。使用外延半导体层将每个半导电体合并在一起。

72. 发明申请

US20110191737A1 GENERATION OF ASYMMETRIC CIRCUIT DEVICES 有权
标题翻译：不对称电路设备的生成
公开(公告)号：US20110191737A1
公开(公告)日：2011-08-04
申请号：US12699621
申请日：2010-02-03
申请人： Leland Chang , Jeffrey W. Sleight
发明人： Leland Chang , Jeffrey W. Sleight
IPC分类号： G06F17/50
CPC分类号： G06F17/50
摘要： A method, system and computer program product are disclosed for creating the appropriate block level shapes to manufacture asymmetric field effect transistors (FETs). In one embodiment, the method comprises obtaining an integrated circuit design having an active region level (RX) and a gate region level (PC), each of the RX and PC levels having a multitude of shapes representing semiconductor regions; and defining a new level SD having a multitude of SD level shapes from the RX and the PC level shapes. This method further comprises identifying which ones of the new shapes are source regions and which ones are drain regions; determining which ones of the source regions are pointing up and which ones are pointing down; and copying the shapes of source regions that are pointing up and the shapes of the source regions that are pointing down onto additional, defined levels.
摘要翻译：公开了一种方法，系统和计算机程序产品，用于创建适当的块级形状以制造不对称场效应晶体管（FET）。在一个实施例中，该方法包括获得具有有源区域电平（RX）和栅极区域电平（PC）的集成电路设计，RX和PC电平中的每一个具有表示半导体区域的多个形状; 并且从RX和PC级形状定义具有多个SD级形状的新级别SD。该方法还包括确定哪些新形状是源区，哪些是形成漏区; 确定哪个源区域正在向上，哪些指向下？并复制向上指向的源区域的形状和指向下一个额定的定义的级别的源区域的形状。

73. 发明申请

US20110065244A1 ASYMMETRIC FINFET DEVICE WITH IMPROVED PARASITIC RESISTANCE AND CAPACITANCE 有权
标题翻译：具有改进的抗电弧和电容的非对称FINFET器件
公开(公告)号：US20110065244A1
公开(公告)日：2011-03-17
申请号：US12559996
申请日：2009-09-15
申请人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Leland Chang , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/66795
摘要： A method for forming a fin field effect transistor (finFET) device includes, forming a fin structure in a substrate, forming a gate stack structure perpendicular to the fin structure, and implanting ions in the substrate at an angle (θ) to form a source region and a drain region in the substrate, wherein the angle (θ) is oblique relative to the source region.
摘要翻译：一种用于形成鳍状场效应晶体管（finFET）器件的方法包括：在衬底中形成翅片结构，形成垂直于翅片结构的栅极堆叠结构，并以一定角度（...）将离子注入到衬底中以形成源极区域和漏极区域，其中角度（θ）相对于源极区域是倾斜的。

74. 发明授权

US07893494B2 Method and structure for SOI body contact FET with reduced parasitic capacitance 有权
标题翻译：具有降低的寄生电容的SOI体接触FET的方法和结构
公开(公告)号：US07893494B2
公开(公告)日：2011-02-22
申请号：US12141276
申请日：2008-06-18
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L27/12
CPC分类号： H01L29/78615 , H01L29/665 , H01L29/66772 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention provides a semiconductor device that includes a substrate including a semiconducting layer positioned overlying an insulating layer the semiconducting layer including a semiconducting body and isolation regions present about a perimeter of the semiconducting body; a gate structure overlying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region.
摘要翻译：在一个实施例中，本发明提供一种半导体器件，其包括衬底，该衬底包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。

75. 发明授权

US07791110B2 Integrated circuit having gates and active regions forming a regular grating 失效
标题翻译：集成电路具有形成规则光栅的栅极和有源区
公开(公告)号：US07791110B2
公开(公告)日：2010-09-07
申请号：US12120878
申请日：2008-05-15
申请人： Leland Chang , Hon-Sum Philip Wong
发明人： Leland Chang , Hon-Sum Philip Wong
IPC分类号： H01L29/80
CPC分类号： H01L27/1104 , H01L27/11
摘要： A semiconductor device includes a plurality of repeatable circuit cells connectable to one or more conductors providing at least electrical connection to the circuit cells and/or electrical connection between one or more circuit elements in the cells. Each of the circuit cells are configured having gates and active regions forming a grating, wherein, for a given active layer in the device, a width of each active region is substantially the same relative to one another, a spacing between any two adjacent active regions is substantially the same, a width of each gate is substantially the same relative to one another, and a spacing between any two adjacent gates is substantially the same.
摘要翻译：半导体器件包括可连接到一个或多个导体的多个可重复的电路单元，至少提供与电路单元的电连接和/或单元中的一个或多个电路元件之间的电连接。每个电路单元被配置成具有栅极和形成光栅的有源区，其中，对于器件中的给定有源层，每个有源区的宽度相对于彼此基本相同，任何两个相邻的有源区之间的间隔基本上相同，每个栅极的宽度相对于彼此基本相同，并且任何两个相邻栅极之间的间隔基本相同。

76. 发明授权

US07785952B2 Partially and fully silicided gate stacks 失效
标题翻译：部分和完全硅化栅极堆叠
公开(公告)号：US07785952B2
公开(公告)日：2010-08-31
申请号：US11873219
申请日：2007-10-16
申请人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
发明人： Leland Chang , Renee Tong Mo , Jeffrey W. Sleight
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/823835 , H01L21/28052 , H01L21/28097 , H01L21/823842 , H01L29/4933 , H01L29/4975
摘要： Metal-oxide semiconductor (MOS) devices and techniques for the fabrication thereof are provided. In one aspect, a metal-oxide semiconductor device is provided comprising a substrate; and at least one n-channel field effect transistor (NFET) having a gate stack over the substrate. The NFET gate stack comprises an NFET gate stack metal gate layer; a first NFET gate stack silicon layer over the NFET gate stack metal gate layer; a second NFET gate stack silicon layer over a side of the first NFET gate stack silicon layer opposite the NFET gate stack metal gate layer, wherein an interface is defined between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer; and an NFET gate stack silicide region that extends through the interface between the first NFET gate stack silicon layer and the second NFET gate stack silicon layer.
摘要翻译：提供了金属氧化物半导体（MOS）器件及其制造技术。一方面，提供一种金属氧化物半导体器件，其包括：衬底; 以及至少一个在衬底上具有栅极堆叠的n沟道场效应晶体管（NFET）。 NFET栅极堆叠包括NFET栅极叠层金属栅极层; 在NFET栅极堆叠金属栅极层上的第一NFET栅极叠层硅层; 在所述第一NFET栅极叠层硅层的与所述NFET栅极堆叠金属栅极层相对的一侧上的第二NFET栅极堆叠硅层，其中在所述第一NFET栅极堆叠硅层和所述第二NFET栅极堆叠硅层之间限定界面; 以及延伸穿过第一NFET栅极堆叠硅层和第二NFET栅极堆叠硅层之间的界面的NFET栅极堆叠硅化物区域。

77. 发明授权

US07736981B2 Metal high dielectric constant transistor with reverse-T gate 失效
标题翻译：具有反T型栅极的金属高介电常数晶体管
公开(公告)号：US07736981B2
公开(公告)日：2010-06-15
申请号：US12113527
申请日：2008-05-01
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L29/72
CPC分类号： H01L29/4908 , H01L21/28114 , H01L29/42384 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833
摘要： A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.
摘要翻译：提供晶体管。晶体管包括包含源极区和漏极区的硅层。栅极堆叠设置在源极区域和漏极区域之间的硅层上。栅堆叠包括高介电常数材料的第一层，包含金属或金属合金的第二层，以及包含硅或多晶硅的第三层。栅极堆叠的第二层的横向范围基本上大于栅极堆叠的第三层的横向范围。还提供了制造这种晶体管的方法。

78. 发明申请

US20100032759A1 SELF-ALIGNED SOI SCHOTTKY BODY TIE EMPLOYING SIDEWALL SILICIDATION 审中-公开
标题翻译：自对准SOI肖特基身体采用侧壁硅酸盐
公开(公告)号：US20100032759A1
公开(公告)日：2010-02-11
申请号：US12189639
申请日：2008-08-11
申请人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Jeffrey W. Sleight
IPC分类号： H01L21/336 , H01L29/786
CPC分类号： H01L29/78612 , H01L29/66772
摘要： A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel formed by the drain and source regions; and a gate oxide layer disposed between the gate region and the channel formed by the drain and source regions, wherein when silicidation is performed on the diffusion region it forms a metal-silicon alloy contact such that the silicide layer extends into and directly touches the channel.
摘要翻译：自对准硅绝缘体（SOI）肖特基体系结构包括：源极区，包括设置在源极区的顶表面上的硅化物层; 漏极区，包括设置在所述漏极区的顶表面上的硅化物层; 栅极区域，设置在由漏极和源极区域形成的沟道上方; 以及栅极氧化物层，其设置在由漏极和源极区域形成的栅极区域和沟道之间，其中当对扩散区域进行硅化时，其形成金属 - 硅合金接触，使得硅化物层延伸到沟道中并直接接触沟道。

79. 发明申请

US20100006956A1 Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same 有权
标题翻译：具有硅侧壁的金属高K晶体管用于减少寄生电容，以及制造相同的工艺
公开(公告)号：US20100006956A1
公开(公告)日：2010-01-14
申请号：US12539842
申请日：2009-08-12
申请人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
发明人： Leland Chang , Isaac Lauer , Renee T. Mo , Jeffrey W. Sleight
IPC分类号： H01L29/78
CPC分类号： H01L29/517 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/6656
摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.
摘要翻译：公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。耗尽的侧壁层是非晶硅或多晶硅之一。该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

80. 发明申请

US20090224335A1 FIELD EFFECT TRANSISTOR WITH REDUCED SHALLOW TRENCH ISOLATION INDUCED LEAKAGE CURRENT 失效
标题翻译：具有减少的低温分离分离诱发的漏电流的场效应晶体管
公开(公告)号：US20090224335A1
公开(公告)日：2009-09-10
申请号：US12041967
申请日：2008-03-04
申请人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
发明人： Leland Chang , Anthony I. Chou , Shreesh Narasimha , Jeffrey W. Sleight
IPC分类号： H01L29/00 , H01L21/336
CPC分类号： H01L29/4238 , H01L29/7833
摘要： Edges of source and drain regions along the direction of a channel of a field effect transistor are formed within an active area offset from the boundary between the active area and a shallow trench isolation structure. Such a structure may be manufactured by forming a gate electrode structure that overlies the boundary so that edges of the source and drain regions are self aligned to the edges of the gate electrode structure on the active area side of the boundary. Unnecessary portions of the gate electrode that does not overlie the source and drain regions may be removed to reduce parasitic capacitance. Shallow trench isolation edge current is eliminated since the semiconductor regions in the current path of the field effect transistor are offset from the boundary between the active area and the shallow trench isolation structure.
摘要翻译：沿场效应晶体管的沟道方向的源极和漏极区域的边缘形成在与有源区域和浅沟槽隔离结构之间的边界偏移的有效区域内。可以通过形成覆盖边界的栅电极结构来制造这种结构，使得源区和漏区的边缘与边界的有源区域侧上的栅电极结构的边缘自对准。可以去除不覆盖源极和漏极区域的栅电极的不必要部分以减小寄生电容。由于场效应晶体管的电流路径中的半导体区域偏离有源区和浅沟槽隔离结构之间的边界，因此消除了浅沟槽隔离边缘电流。

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