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71. 发明申请

US20060206852A1 System and method for designing semiconductor photomasks 有权
标题翻译：设计半导体光掩模的系统和方法
公开(公告)号：US20060206852A1
公开(公告)日：2006-09-14
申请号：US11078820
申请日：2005-03-10
申请人： Andrew Khoh , Byong-Il Choi , Lap Chan , Ganesh Samudra , Yihong Wu
发明人： Andrew Khoh , Byong-Il Choi , Lap Chan , Ganesh Samudra , Yihong Wu
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A trial semiconductor photomask design having discontinuity points is provided, and each of the discontinuity points is treated as simulated light sources. Simulated light from each of the simulated light sources is focused, and a composite image intensity of the focused simulated light is calculated to verify the trial semiconductor photomask design. The trial semiconductor photomask design is sharpened. A photomask design specification is generated for use in fabricating such a photomask.
摘要翻译：提供具有不连续点的试验半导体光掩模设计，将每个不连续点视为模拟光源。聚焦每个模拟光源的模拟光，并计算聚焦模拟光的合成图像强度，以验证试验半导体光掩模设计。试制半导体光掩模设计锐化。生成光掩模设计规范用于制造这种光掩模。

72. 发明申请

US20060194397A1 Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates 审中-公开
公开(公告)号：US20060194397A1
公开(公告)日：2006-08-31
申请号：US11391506
申请日：2006-03-28
申请人： Lay Choo , James Lee , Lap Chan
发明人： Lay Choo , James Lee , Lap Chan
IPC分类号： H01L21/336
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76895 , H01L21/823481 , Y10S438/949
摘要： In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

73. 发明授权

US07060573B2 Extended poly buffer STI scheme 失效
公开(公告)号：US07060573B2
公开(公告)日：2006-06-13
申请号：US09759909
申请日：2001-01-16
申请人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
发明人： Victor Seng Keong Lim , Feng Chen , Lap Chan , Wang Ling Goh
IPC分类号： H01L21/336
CPC分类号： H01L21/76232
摘要： A new method of forming shallow trench isolations has been described. A silicon semiconductor substrate is provided. A silicon nitride layer is deposited overlying the substrate. A polysilicon layer is deposited overlying the silicon nitride layer. An oxidation mask is deposited overlying the polysilicon layer. The oxidation mask, polysilicon layer, silicon nitride layer, and the silicon semiconductor substrate are patterned to form trenches for planned shallow trench isolations. The silicon semiconductor substrate exposed within the trenches is oxidized to form an oxide liner layer within the trenches wherein the oxidation mask prevents oxidation of the polysilicon layer. Thereafter the oxidation mask is removed. A trench oxide layer is deposited overlying the liner oxide layer and filling the trenches. The trench oxide layer and the polysilicon layer are polished down stopping at the silicon nitride layer with a polishing selectivity of oxide to polysilicon to nitride of 4:100:1 wherein dishing is avoided to complete shallow trench isolations in the manufacture of an integrated circuit device.

74. 发明授权

US07037791B2 Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates 失效
公开(公告)号：US07037791B2
公开(公告)日：2006-05-02
申请号：US10135071
申请日：2002-04-30
申请人： Lay Cheng Choo , James Yong Meng Lee , Lap Chan
发明人： Lay Cheng Choo , James Yong Meng Lee , Lap Chan
IPC分类号： H01L21/336 , G03C5/00 , G03C5/16
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76895 , H01L21/823481 , Y10S438/949
摘要： In accordance with the objects of this invention, a new method of fabricating a polysilicon gate transistor is achieved. An alternating aperture phase shift mask (AAPSM) is used to pattern polysilicon gates in a single exposure without a trim mask. A semiconductor substrate is provided. A gate dielectric layer is deposited. A polysilicon layer is deposited. The polysilicon layer, the gate dielectric layer and the semiconductor substrate are patterned to form trenches for planned shallow trench isolations (STI). A trench oxide layer is deposited filling the trenches. The trench oxide layer is polished down to the top surface of the polysilicon layer to complete the STI. A photoresist layer is deposited and patterned to form a feature mask for planned polysilicon gates. The patterning is by a single exposure using an AAPSM mask. Unwanted features in the photoresist pattern that are caused by phase conflicts overlie the STI. The polysilicon layer is etched to form the polysilicon gates.

75. 发明申请

US20050074939A1 Process to manufacture nonvolatile MOS memory device 有权
标题翻译：制造非易失性MOS存储器件的工艺
公开(公告)号：US20050074939A1
公开(公告)日：2005-04-07
申请号：US10676896
申请日：2003-10-01
申请人： Vincent Ho , Wee Choi , Lap Chan , Wai Chim , Vivian Ng , Cheng Heng , Lee Teo
发明人： Vincent Ho , Wee Choi , Lap Chan , Wai Chim , Vivian Ng , Cheng Heng , Lee Teo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8242 , H01L29/423 , H01L29/788
CPC分类号： B82Y10/00 , H01L21/28282 , H01L29/42332 , H01L29/7881 , Y10S438/962
摘要： Devices with embedded silicon or germanium nanocrystals, fabricated using ion implantation, exhibit superior data-retention characteristics relative to conventional floating-gate devices. However, the prior art use of ion implantation for their manufacture introduces several problems. These have been overcome by initial use of rapid thermal oxidation to grow a high quality layer of thin tunnel oxide. Chemical vapor deposition is then used to deposit a germanium doped oxide layer. A capping oxide is then deposited following which the structure is rapid thermally annealed to synthesize the germanium nanocrystals.
摘要翻译：使用离子注入制造的具有嵌入式硅或锗纳米晶体的器件相对于常规浮栅器件表现出优异的数据保持特性。然而，现有技术中使用离子注入来制造这些问题。通过初始使用快速热氧化来生长高质量的薄隧道氧化物层，已经克服了这些。然后使用化学气相沉积来沉积掺锗的氧化物层。然后沉积封端氧化物，然后将结构快速热退火以合成锗纳米晶体。

76. 发明授权

US06835631B1 Method to enhance inductor Q factor by forming air gaps below inductors 有权
标题翻译：通过在电感器下方形成气隙来增强电感Q因子的方法
公开(公告)号：US06835631B1
公开(公告)日：2004-12-28
申请号：US10718193
申请日：2003-11-20
申请人： Zheng Jia Zhen , Sanford Chu , Ng Chit Hwei , Lap Chan , Purakh Raj Verma
发明人： Zheng Jia Zhen , Sanford Chu , Ng Chit Hwei , Lap Chan , Purakh Raj Verma
IPC分类号： H01L2120
CPC分类号： H01L28/10 , H01L23/5222 , H01L23/5227 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.
摘要翻译：一种提高电感器性能的方法，包括以下步骤。提供一种其上形成有第一氧化物层的结构。在第一氧化物层上形成较低的低k电介质层。在下部低k电介质层上形成第二氧化物层。图案化第二氧化物层以通过暴露下部低k电介质层的一部分而在其中形成至少一个孔。通过下部低k介电层的暴露部分蚀刻到下部低k电介质层中，从而蚀刻下蚀刻的低k介电层内的至少一个相应的气隙。在图案化的第二氧化物层上形成上部低k电介质层。至少一个电感器形成在上部低k电介质层内并在至少一个气隙上形成，从而提高了电感器的性能。

77. 发明授权

US06777774B2 Low noise inductor using electrically floating high resistive and grounded low resistive patterned shield 有权
标题翻译：低噪声电感使用电浮动高电阻和接地的低电阻图案屏蔽
公开(公告)号：US06777774B2
公开(公告)日：2004-08-17
申请号：US10125244
申请日：2002-04-17
申请人： Sia Choon Beng , Yeo Kiat Seng , Sanford Chu , Lap Chan , Chew Kok-Wai
发明人： Sia Choon Beng , Yeo Kiat Seng , Sanford Chu , Lap Chan , Chew Kok-Wai
IPC分类号： H01L2900
CPC分类号： H01L28/10 , H01L23/552 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A novel complimentary shielded inductor on a semiconductor is disclosed. A region of electrically floating high resistive material is deposited between the inductor and the semiconductor substrate. The high resistive shield is patterned with a number of gaps, such that a current induced in the shield by the inductor does not have a closed loop path. The high resistive floating shield compliments a grounded low resistive shield to achieve higher performance inductors. In this fashion, noise in the substrate is reduced. The novel complimentary shield does not significantly degrade the figures of merit of the inductor, such as, quality factor and resonance frequency. In one embodiment, the grounded shield is made of patterned N-well (or P-well) structures. In still another embodiment, the low resistive electrically grounded shield is made of patterned Silicide, which may be formed on portions of the substrate itself.
摘要翻译：公开了一种半导体上的新型有用屏蔽电感器。电浮动高电阻材料的区域沉积在电感器和半导体衬底之间。高电阻屏蔽层被图案化为多个间隙，使得由电感器在屏蔽层中感应的电流不具有闭环路径。高电阻浮动屏蔽补充了接地的低电阻屏蔽以实现更高性能的电感器。以这种方式，衬底中的噪声降低。新型互补屏蔽不会显着降低电感器的品质因数，如品质因数和谐振频率。在一个实施例中，接地屏蔽由图案化的N阱（或P阱）结构制成。在另一个实施例中，低电阻电接地屏蔽由图案化的硅化物制成，其可以形成在衬底本身的部分上。

78. 发明授权

US06566650B1 Incorporation of dielectric layer onto SThM tips for direct thermal analysis 失效
标题翻译：将介电层并入SThM尖端进行直接热分析
公开(公告)号：US06566650B1
公开(公告)日：2003-05-20
申请号：US09664418
申请日：2000-09-18
申请人： Chang Chaun Hu , Kin Leong Pey , Yung Fu Chong , Chim Wai Kin , Pavel Neuzil , Lap Chan
发明人： Chang Chaun Hu , Kin Leong Pey , Yung Fu Chong , Chim Wai Kin , Pavel Neuzil , Lap Chan
IPC分类号： B01D5944
CPC分类号： G01Q60/58 , Y10S977/867 , Y10S977/875
摘要： One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive current leakage between the tip and the conductive sample. The present invention eliminates the need for this by coating the probe's microtip with a layer of insulation that is also a good thermal conductor. Examples of both thermocouple and thermistor based probes are given along with processes for their manufacture.
摘要翻译：当需要获得电偏置样本的热图时，会出现当前使用扫描热显微镜的局限性。目前的做法是使样品的导电部件被钝化，以防止尖端和导电样品之间的过大的电流泄漏。本发明通过用也是良好热导体的绝缘层涂覆探针的微尖头来消除对此的需要。给出了热电偶和基于热敏电阻的探针的实例以及其制造方法。

79. 发明授权

US06544824B1 Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel 失效
标题翻译：通过首先形成栅/间隔堆叠形成垂直晶体管的方法，然后使用选择性外延形成源极，漏极和沟道
公开(公告)号：US06544824B1
公开(公告)日：2003-04-08
申请号：US10038390
申请日：2002-01-03
申请人： Yelehanka Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung
发明人： Yelehanka Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Lee Yong Meng , Ying Keung
IPC分类号： H01L2100
CPC分类号： H01L29/66666
摘要： A method of manufacturing a vertical transistor. A doped region is formed in a substrate. We form sequentially on the substrate: a first spacer dielectric layer, a first gate electrode, a second spacer dielectric layer, a second gate electrode and a third spacer dielectric layer. A trench is formed through the first spacer dielectric layer, the first gate electrode, the second spacer dielectric layer, the second gate electrode and the third spacer dielectric layer. The trench has sidewalls. A gate dielectric layer is formed over the sidewalls of the trench. We form sequentially, in the trench: a first doped layer, a first channel layer, a second doped layer, a third doped layer, a second channel layer, and a fourth doped layer. A cap layer is formed over the structure. Contacts are preferably formed to the doped region, doped layers and gate electrodes.
摘要翻译：一种垂直晶体管的制造方法。在衬底中形成掺杂区域。我们在衬底上依次形成：第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层。通过第一间隔电介质层，第一栅电极，第二间隔电介质层，第二栅电极和第三间隔电介质层形成沟槽。沟槽有侧壁。栅极电介质层形成在沟槽的侧壁上。我们在沟槽中依次形成：第一掺杂层，第一沟道层，第二掺杂层，第三掺杂层，第二沟道层和第四掺杂层。在该结构上形成盖层。触点优选地形成于掺杂区域，掺杂层和栅电极。

80. 发明授权

US06468877B1 Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner 有权
标题翻译：通过使用一次性间隔件/衬垫在栅电极的边缘下形成气隙的方法
公开(公告)号：US06468877B1
公开(公告)日：2002-10-22
申请号：US09907651
申请日：2001-07-19
申请人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
发明人： Yelehanka Ramachandramurthy Pradeep , Jia Zhen Zheng , Lap Chan , Elgin Quek , Ravi Sundaresan , Yang Pan , James Yong Meng Lee , Ying Keung Leung
IPC分类号： H01L2176
CPC分类号： H01L21/7682 , H01L21/764 , H01L21/823468 , H01L29/4983
摘要： A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode. The planarized thick oxide layer is removed with a portion of the liner oxide layer and a portion of the gate dielectric layer under the gate electrode to form a cross-section inverted T-shaped opening on either side of the gate electrode. A gate spacer oxide layer is formed over the structure at least as thick as the gate electrode, wherein the gate spacer oxide layer partially fills the inverted T-shaped opening from the top down and wherein air gap spacers are formed proximate the bottom of the inverted T-shaped opening. The gate spacer oxide, liner nitride, and liner oxide layers are etched to form gate spacers proximate the gate electrode. The gate spacers having an underlying etched liner nitride layer and liner oxide layer.
摘要翻译：一种制造半导体器件的气隙间隔物的方法，包括以下步骤。提供具有至少一对限定有源区域的STI的半导体衬底。在有源区内的基板上形成栅电极。栅电极具有底层栅介电层。在该结构上形成衬里氧化物层，覆盖栅极电介质层的侧壁，栅电极以及栅电极的顶表面。在衬垫氧化物层上形成衬里氮化物层。在结构上形成厚的氧化物层。厚氧化物，衬里氮化物和衬里氧化物层与栅电极的顶表面平坦化，并且在栅电极的任一侧暴露衬里氧化物层。用一部分衬垫氧化物层和栅电介质层的一部分在栅电极下方去除平坦化的厚氧化物层，以在栅电极的任一侧上形成横截面倒置的T形开口。在该结构上形成至少与栅电极一样厚的栅极间隔氧化物层，其中栅极间隔物氧化物层从顶部向下部分地填充倒置的T形开口，并且其中气隙间隔物邻近倒置的底部形成 T形开口。蚀刻栅间隔氧化物，衬里氮化物和衬里氧化物层以在栅电极附近形成栅极间隔。栅极间隔物具有下面的蚀刻衬里氮化物层和衬里氧化物层。

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