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71. 发明授权

US5959481A Bus driver circuit including a slew rate indicator circuit having a one shot circuit 失效
标题翻译：总线驱动器电路包括具有单触发电路的转换速率指示器电路
公开(公告)号：US5959481A
公开(公告)日：1999-09-28
申请号：US801521
申请日：1997-02-18
申请人： Kevin S. Donnelly , Chanh Tran , Michael Ching , Bruno Garlepp
发明人： Kevin S. Donnelly , Chanh Tran , Michael Ching , Bruno Garlepp
IPC分类号： G06F13/40 , H03K5/12
CPC分类号： G06F13/4072
摘要： A bus driver circuit having slew rate control. According to one embodiment, the bus driver circuit includes the following elements: a first circuit having an input configured to receive a data signal and an output operative to output a drive signal in response to the data signal; a second circuit coupled in parallel with the first circuit and operative to receive a slew rate control signal; and a slew rate indicator circuit coupled to the second circuit. The slew rate indicator circuit determines the state of the slew rate control signal in response to operating conditions that cause variations in the slew rate of the drive signal such that when the slew rate control signal is asserted, the second circuit is enabled to affect the slew rate of the drive signal. For one embodiment, the slew rate indicator includes a pulse generator circuit and a clocked comparator circuit. The pulse generator circuit is operative to receive a clock signal and generate a pulse in response to a first transition of the clock signal. The clocked comparator is coupled to the pulse generator circuit and operative to receive the pulse. The clocked comparator determines the state of the slew rate control signal by sampling for the pulse in response to a second transition of the clock signal.
摘要翻译：具有转换速率控制的总线驱动器电路。根据一个实施例，总线驱动器电路包括以下元件：第一电路，其具有被配置为接收数据信号的输入和用于响应于数据信号输出驱动信号的输出; 第二电路，与第一电路并联并且可操作以接收压摆率控制信号; 以及耦合到第二电路的转换速率指示器电路。压摆率指示电路响应于导致驱动信号的转换速率的变化的操作条件来确定转换速率控制信号的状态，使得当转换速率控制信号被确认时，第二电路能够影响转换驱动信号的速率。对于一个实施例，转换速率指示器包括脉冲发生器电路和时钟比较器电路。脉冲发生器电路用于接收时钟信号并且响应于时钟信号的第一转换而产生脉冲。时钟比较器耦合到脉冲发生器电路并且可操作以接收脉冲。时钟比较器响应于时钟信号的第二次转换来确定脉冲采样的转换速率控制信号的状态。

72. 发明授权

US5621340A Differential comparator for amplifying small swing signals to a full swing output 失效
标题翻译：用于将小摆动信号放大到全摆幅输出的差分比较器
公开(公告)号：US5621340A
公开(公告)日：1997-04-15
申请号：US510141
申请日：1995-08-02
申请人： Thomas H. Lee , Kevin S. Donnelly
发明人： Thomas H. Lee , Kevin S. Donnelly
IPC分类号： H03F3/72 , H03K3/356 , H03K5/24 , H03K17/10 , H03F3/45 , H03K17/04
CPC分类号： H03K5/249 , H03F3/72 , H03K3/356121 , H03K5/2481
摘要： A differential comparator that amplifies small swing signals to full swing signals. The differential comparator comprises a current switch having a pair of inputs coupled to receive a pair of small swing complementary input signals and a pair of complementary outputs that output complementary signals. The complementary signals output by the current switch have a voltage swing that centers about a predetermined voltage in response to the complementary input signals. The differential comparator further comprises first and second inverters coupled to receive the output complementary signals, wherein each inverter has a trip point voltage equal to the predetermined voltage. The first and second inverters output full swing complementary output signals in response to the complementary signals output by the current switch.
摘要翻译：将小摆幅信号放大到全摆幅信号的差分比较器。差分比较器包括电流开关，其具有耦合以接收一对小摆动互补输入信号的一对输入和输出互补信号的一对互补输出。由电流开关输出的互补信号具有响应于互补输入信号而围绕预定电压中心的电压摆幅。差分比较器还包括耦合以接收输出互补信号的第一和第二反相器，其中每个反相器具有等于预定电压的跳变点电压。第一和第二反相器响应于电流开关输出的互补信号输出全摆幅互补输出信号。

73. 发明授权

US5554945A Voltage controlled phase shifter with unlimited range 失效
标题翻译：电压控制移相器，无限范围
公开(公告)号：US5554945A
公开(公告)日：1996-09-10
申请号：US196582
申请日：1994-02-15
申请人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho
发明人： Thomas H. Lee , Kevin S. Donnelly , Tsyr-Chyang Ho
IPC分类号： H03H11/20 , H03K5/13
CPC分类号： H03H11/20 , H03K2005/00286
摘要： A voltage-controlled phase shift apparatus having an unlimited range for producing an output signal that varies in phase from an input signal by a predetermined phase difference. The phase shift apparatus includes a first delay circuit coupled to receive the input signal, the first delay circuit for outputting a first intermediate signal that is .alpha. degrees out of phase with the input signal, a second intermediate signal that is .beta. degrees out of phase with the first intermediate signal, a third intermediate signal that is 180 degrees out of phase with the first intermediate signal, and a fourth intermediate signal that is 180 degrees out of phase with the second intermediate signal. The phase shift apparatus also includes a phase interpolator circuit coupled to receive a control voltage signal and the first, second, third and fourth intermediate signals, the phase interpolator for phase mixing a selected pair of the first, second, third and fourth intermediate signals in response to the control voltage signal, the phase interpolator for outputting the output signal. A phase selector circuit coupled to the phase interpolator circuit and coupled to receive a phase slope signal and the control voltage signal selects the selected pair in response to the phase slope signal and the control voltage signal such that the output signal varies in phase from the input signal by the predetermined phase difference.
摘要翻译：一种具有无限范围的电压控制相移装置，用于产生与输入信号相位相差预定相位差的输出信号。相移装置包括耦合以接收输入信号的第一延迟电路，用于输出与输入信号异相异步的第一中间信号的第一延迟电路，与相位相差β度的第二中间信号，第一中间信号，与第一中间信号相差180度的第三中间信号，以及与第二中间信号相差180度的第四中间信号。相移装置还包括相位插值器电路，其耦合以接收控制电压信号和第一，第二，第三和第四中间信号，相位内插器，用于将所选择的一对第一，第二，第三和第四中间信号相互混合在对控制电压信号的响应，用于输出输出信号的相位插值器。相位选择器电路，耦合到所述相位内插器电路并被耦合以接收相位斜率信号，并且所述控制电压信号响应于所述相位斜率信号和所述控制电压信号选择所选择的对，使得所述输出信号与所述输入信号信号预定的相位差。

74. 发明授权

US09553745B2 High-speed signaling systems with adaptable pre-emphasis and equalization 有权
标题翻译：具有适应性预加重和均衡的高速信号系统
公开(公告)号：US09553745B2
公开(公告)日：2017-01-24
申请号：US13452513
申请日：2012-04-20
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian Leibowitz
IPC分类号： H04L27/01 , H04L1/00 , H04L7/033 , H04L25/03 , H04L25/497 , H04W52/20 , H04L7/00 , H04L25/02 , H04W52/22
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.
摘要翻译：一个信令系统包括一个预先强调的发射机和一个通过高速信号路径相互耦合的均衡接收机。接收机测量从发射机传送的数据的质量。控制器使用该信息和其他信息来自适应地建立适当的发送预加重和接收均衡设置，例如，选择信令系统提供一些最小通信带宽而不超过所需误码率的最低功率设置。

75. 发明授权

US08630317B2 Memory system with calibrated data communication 有权
标题翻译：具有校准数据通信的存储系统
公开(公告)号：US08630317B2
公开(公告)日：2014-01-14
申请号：US13447080
申请日：2012-04-13
申请人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
发明人： Jared LeVan Zerbe , Kevin S. Donnelly , Stefanos Sidiropoulos , Donald C. Stark , Mark A. Horowitz , Leung Yu , Roxanne Vu , Jun Kim , Bruno W. Garlepp , Tsyr-Chyang Ho , Benedict Chung-Kwong Lau
IPC分类号： H04J3/06 , G06F1/12
CPC分类号： G06F13/364 , G06F1/10 , G06F3/061 , G06F3/0659 , G06F3/0679 , G06F12/0246 , G06F13/1689 , G06F13/1694 , G06F13/404 , G06F13/4243 , G06F13/4282 , G06F2212/7201 , G06F2212/7207 , G11C7/1045 , H04L7/0008 , H04L7/033
摘要： An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.
摘要翻译：集成电路装置包括发射机电路，其可操作以通过第一导线将定时信号发送到DRAM。 DRAM接收具有平衡数量的逻辑零到一转换和一到零转换的第一信号，并且在定时信号的上升沿采样第一信号以产生相应的采样值。该装置还包括一个接收器电路，用于从与第一线分开的多个线上的DRAM接收相应的采样值。在第一模式中，发射机电路重复地将定时信号的增量偏移版本发送到DRAM，直到从DRAM接收到的采样值从逻辑0变为逻辑0，反之亦然; 并且在第二模式中，它根据基于采样值产生的写定时偏移，将多条线上的写数据发送到DRAM。

76. 发明授权

US08497544B2 Repairing defects in a nonvolatile semiconductor memory module utilizing a heating element 失效
标题翻译：利用加热元件修复非易失性半导体存储器模块中的缺陷
公开(公告)号：US08497544B2
公开(公告)日：2013-07-30
申请号：US13486977
申请日：2012-06-01
申请人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
发明人： Gary B. Bronner , Ming Li , Donald R. Mullen , Frederick Ware , Kevin S. Donnelly
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： G11C16/349 , G11C16/3418 , H01L23/3128 , H01L23/345 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2924/15311 , H01L2924/19107 , H01L2924/00012 , H01L2924/00
摘要： A memory module includes multiple memory devices mounted to a substrate and one or more discrete heating elements disposed in thermal contact with the memory devices. Each of the memory devices includes charge-storing memory cells subject to operation-induced defects that degrade ability of the memory cells to store data. The discrete heating elements, or single discrete heating element, heats the memory devices to a temperature that anneals the defects.
摘要翻译：存储器模块包括安装到基板的多个存储器件和与存储器件热接触地设置的一个或多个分立加热元件。每个存储器件包括经受操作引起的缺陷的电荷存储存储单元，其使存储器单元存储数据的能力降低。离散加热元件或单独的分立加热元件将存储器件加热到退火缺陷的温度。

77. 发明授权

US08458385B2 Chip having register to store value that represents adjustment to reference voltage 有权
标题翻译：具有寄存器的芯片存储表示对参考电压的调整的值
公开(公告)号：US08458385B2
公开(公告)日：2013-06-04
申请号：US13535228
申请日：2012-06-27
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00 , G05F1/10
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.
摘要翻译：芯片包括接收器电路，其使用参考电压来接收数据信号，使得使用参考电压确定接收到的数据信号的逻辑电平，以及寄存器，用于存储表示对参考电压的调整的值。

78. 发明授权

US08344475B2 Integrated circuit heating to effect in-situ annealing 有权
标题翻译：集成电路加热实现原位退火
公开(公告)号：US08344475B2
公开(公告)日：2013-01-01
申请号：US12859554
申请日：2010-08-19
申请人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
发明人： Ian P. Shaeffer , Gary B. Bronner , Brent S. Haukness , Kevin S. Donnelly , Frederick A. Ware , Mark A. Horowitz
IPC分类号： H01L29/00
CPC分类号： G11C16/26 , G11C7/04 , G11C13/0002 , G11C13/0033 , G11C13/0035 , G11C16/06 , H01L21/324
摘要： In a system having a memory device, an event is detected during system operation. The memory device is heated to reverse use-incurred degradation of the memory device in response to detecting the event. In another system, the memory device is heated to reverse use-incurred degradation concurrently with execution of a data access operation within another memory device of the system. In another system having a memory controller coupled to first and second memory devices, data is evacuated from the first memory device to the second memory device in response to determining that a maintenance operation is needed within the first memory device.
摘要翻译：在具有存储器件的系统中，在系统操作期间检测到事件。响应于检测到事件，存储器件被加热以反转存储器件的使用中的劣化。在另一系统中，存储器件被加热以与系统的另一个存储器件内的数据访问操作的执行同时反向使用所引起的降级。在具有耦合到第一和第二存储器设备的存储器控制器的另一系统中，响应于确定在第一存储器设备内需要维护操作，将数据从第一存储器设备抽出到第二存储器设备。

79. 发明申请

US20120268199A1 Chip Having Register to Store Value that Represents Adjustment to Reference Voltage 有权
标题翻译：芯片有注册存储代表调整参考电压的值
公开(公告)号：US20120268199A1
公开(公告)日：2012-10-25
申请号：US13535228
申请日：2012-06-27
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： H01L25/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： A chip includes a receiver circuit that uses a reference voltage to receive a data signal such that a logic level of the received data signal is determined using the reference voltage, and a register to store a value that represents an adjustment to the reference voltage.
摘要翻译：芯片包括接收器电路，其使用参考电压来接收数据信号，使得使用参考电压确定接收到的数据信号的逻辑电平，以及寄存器，用于存储表示对参考电压的调整的值。

80. 发明申请

US20120207196A1 High-Speed Signaling Systems with Adaptable Pre-Emphasis and Equalization 有权
公开(公告)号：US20120207196A1
公开(公告)日：2012-08-16
申请号：US13452513
申请日：2012-04-20
申请人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian Leibowitz
发明人： Jared L. Zerbe , Fred F. Chen , Andrew Ho , Ramin Farjad-Rad , John W. Poulton , Kevin S. Donnelly , Brian Leibowitz
IPC分类号： H04L27/01 , H04B15/00 , H04B17/00 , H04B1/38
CPC分类号： H04L27/01 , H04L1/0026 , H04L7/0025 , H04L7/0087 , H04L7/0337 , H04L25/0272 , H04L25/028 , H04L25/03057 , H04L25/03343 , H04L25/03885 , H04L25/497 , H04L2025/03503 , H04W52/20 , H04W52/225 , Y02D70/00
摘要： A signaling system includes a pre-emphasizing transmitter and an equalizing receiver coupled to one another via a high-speed signal path. The receiver measures the quality of data conveyed from the transmitter. A controller uses this information and other information to adaptively establish appropriate transmit pre-emphasis and receive equalization settings, e.g. to select the lowest power setting for which the signaling system provides some minimum communication bandwidth without exceeding a desired bit-error rate.

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