会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 72. 发明申请
    • INERTIAL SENSOR AND INERTIAL DETECTING DEVICE
    • 惯性传感器和惯性检测装置
    • US20090322183A1
    • 2009-12-31
    • US12488691
    • 2009-06-22
    • Takashi KawakuboToshihiko NaganoMichihiko Nishigaki
    • Takashi KawakuboToshihiko NaganoMichihiko Nishigaki
    • G01P15/09
    • G01P15/09G01C19/5621G01C19/5628G01C19/5656G01P15/0922G01P15/18G01P2015/0817G01P2015/0828
    • An inertial sensor includes a first beam, a first proof mass section and a first upper surface stopper section. The first beam extends in a first direction in a plane parallel to a major surface of a substrate and is held with a spacing from the major surface of the substrate. The first beam has a first detecting section including a first upper side electrode, a first lower side electrode, and a first upper side piezoelectric film provided between the first upper side electrode and the first lower side electrode. The first beam has one end connected to the major surface of the substrate. The first proof mass section is connected to the other end of the first beam and held with a spacing from the major surface of the substrate. The first upper surface stopper section is provided on the opposite side of the first proof mass section from the substrate with a spacing from the first proof mass section.
    • 惯性传感器包括第一光束,第一检测质量部分和第一上表面阻挡部分。 第一光束在与基板的主表面平行的平面中沿第一方向延伸,并且与基板的主表面保持间隔。 第一光束具有包括设置在第一上侧电极和第一下侧电极之间的第一上侧电极,第一下侧电极和第一上侧压电膜的第一检测部。 第一光束的一端连接到基板的主表面。 第一检测质量部分连接到第一光束的另一端并且与衬底的主表面间隔保持。 第一上表面止动部分设置在第一检验质量部分的与第一检验质量部分间隔开的基板的相对侧上。
    • 78. 发明授权
    • Non-volatile semiconductor integrated memory device
    • 非易失性半导体集成存储器件
    • US06198652B1
    • 2001-03-06
    • US09289940
    • 1999-04-13
    • Takashi KawakuboKazuhide AbeDaisaburo Takashima
    • Takashi KawakuboKazuhide AbeDaisaburo Takashima
    • G11C1122
    • H01L27/11502G11C11/22G11C11/223
    • A semiconductor integrated memory device comprises a plurality of memory cell blocks, which are formed in the form of a matrix and each of which comprises: a memory cell chain including a plurality of units, each comprising a ferroelectric memory capacitor and a control transistor connected in parallel thereto; a reference capacitor of a unit comprising a reference capacitor and a control transistor connected in parallel thereto; a read transistor having a gate electrode connected to a connection point between the memory cell chain and the reference cell; and a control transistor for adjusting potentials of storage node which is a connection point of the first electrode of the memory capacitor, the third electrode of the reference capacitor and the read transistor. With this construction, the semiconductor integrated memory device is able to be easily produced, to stably retain a ferroelectric polarization and to scale down.
    • 半导体集成存储器件包括以矩阵形式形成的多个存储器单元块,每个存储单元块包括:包括多个单元的存储单元链,每个单元包括铁电存储电容器和连接在其上的控制晶体管 平行于 包括参考电容器和与其并联连接的控制晶体管的单元的参考电容器; 读取晶体管,其具有连接到存储器单元链和参考单元之间的连接点的栅电极; 以及用于调整作为存储电容器的第一电极,参考电容器的第三电极和读取晶体管的连接点的存储节点的电位的控制晶体管。 利用这种结构,能够容易地制造半导体集成存储器件,以稳定地保持铁电极化并缩小。
    • 80. 发明授权
    • Electronic parts and manufacturing method thereof
    • 电子零件及其制造方法
    • US06001461A
    • 1999-12-14
    • US771388
    • 1996-12-19
    • Hiroshi ToyodaHisashi KanekoMasahiko HasunumaTakashi KawanoueHiroshi TomitaAkihiro KajitaMasami MiyauchiTakashi KawakuboSachiyo Ito
    • Hiroshi ToyodaHisashi KanekoMasahiko HasunumaTakashi KawanoueHiroshi TomitaAkihiro KajitaMasami MiyauchiTakashi KawakuboSachiyo Ito
    • H01L21/3205H01L23/528H01L23/532B32B9/00
    • H01L23/532H01L21/32051H01L23/5283H01L23/53223H01L2924/0002Y10T428/2457Y10T428/24926
    • An electronic part comprising an amorphous thin film formed on a substrate; and a metal wiring formed on the surface of the amorphous thin film; wherein an interatomic distance corresponding to a peak of halo pattern appearing in diffraction measurement of the amorphous thin film approximately matches with a spacing of a particular crystal plane defined with the first nearest interatomic distance of the metal wiring. An electronic part provided with a metal wiring formed of highly orientated crystal wherein half or more of all grain boundaries are small angle grain boundaries defined by one of grain boundaries with a relative misorientation of 10.degree. or less in tilt, rotation and combination thereof around orientation axes of neighboring crystal grains; coincidence boundaries where a .SIGMA. value is 10 or less; and grain boundaries with a relative misorientation of 3.degree. or less from the coincidence boundary. A method for manufacturing an electronic part, comprising the step of depositing a conductor layer which is mainly formed of one selected from Al and Cu on a substrate via an insulative layer, a barrier layer, a contact layer or an amorphous thin film layer wherein one element selected from Ga, In, Cd, Bi, Pb, Sn and Tl is supplied before or during the deposition of the conductor layer.
    • 一种电子部件,包括形成在基板上的非晶薄膜; 以及形成在所述非晶薄膜的表面上的金属布线; 其中对应于在非晶薄膜的衍射测量中出现的晕轮图案的峰值的原子间距离大致与由金属布线的第一最接近的原子间距离限定的特定晶面的间隔相匹配。 一种电子部件,其具有由高取向晶体形成的金属布线,其中所有晶界的一半以上是由倾斜,旋转及其组合在取向方向上的相位差取向为10°以下的晶界之一限定的小角度晶界 相邻晶粒的轴; SIGMA值为10以下的重合边界; 晶界与重合边界的相对误差为3°以下。 一种电子部件的制造方法,其特征在于,包括以下步骤:通过绝缘层,阻挡层,接触层或无定形薄膜层,在基板上沉积主要由选自Al和Cu的一个导体层形成的步骤,其中一个 选自Ga,In,Cd,Bi,Pb,Sn和Tl的元素在导体层的沉积之前或期间提供。