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71. 发明授权

US06794226B2 Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication 有权
$Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication$
标题翻译：掺入由难熔金属硅 - 氮形成的元件的半导体器件及其制造方法
公开(公告)号：US06794226B2
公开(公告)日：2004-09-21
申请号：US10374395
申请日：2003-02-26
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2182
CPC分类号： H01L21/76849 , H01L21/7687 , H01L21/76888 , H01L23/5258 , H01L27/0629 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.
摘要翻译：公开了一种半导体结构，其包括由难熔金属 - 硅 - 氮形成的熔丝，扩散阻挡层或电容器的至少一个电路元件。还公开了一种通过难熔金属硅 - 氮材料制造这种半导体结构的方法，其包括熔丝元件，扩散阻挡层，电阻器或电容器。要使用的合适的难熔金属 - 硅 - 氮材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。本发明提供了通过TaSiN层的单个沉积工艺可以形成扩散阻挡层，保险丝，电容器和电阻器的各种组件的优点，然后通过热处理或离子注入对各种组分进行选择性掩蔽和处理，选择性地改变其电阻率，同时保持其他屏蔽元件具有相同的电阻率。

72. 发明授权

US06541331B2 Method of manufacturing high dielectric constant material 失效
标题翻译：制造高介电常数材料的方法
公开(公告)号：US06541331B2
公开(公告)日：2003-04-01
申请号：US09924548
申请日：2001-08-09
申请人： Michael P. Chudzik , Lawrence Clevenger , Louis L. Hsu , Deborah A. Neumayer , Joseph F. Shepard, Jr.
发明人： Michael P. Chudzik , Lawrence Clevenger , Louis L. Hsu , Deborah A. Neumayer , Joseph F. Shepard, Jr.
IPC分类号： H01L218242
CPC分类号： C23C16/45525 , C23C16/40 , C23C16/56 , H01L21/02178 , H01L21/02192 , H01L21/02194 , H01L21/0228 , H01L21/02304 , H01L21/31604 , H01L21/3162
摘要： A process of forming a high-k dielectric in an integrated circuit structure is disclosed. The process cleans a substrate to remove residual organic materials and strip native oxide from the surface of the substrate. Next, the process introduces precursors on the substrate in molar ratios consistent with formation of dielectric glass films. Following that, the process oxidizes the precursors, heats the precursors, and cools the precursors at a rate that avoids crystallization of the precursors.
摘要翻译：公开了一种在集成电路结构中形成高k电介质的工艺。该方法清洗基材以除去残余的有机材料并从基材的表面剥离天然氧化物。接下来，该方法以与电介质玻璃膜的形成一致的摩尔比在基材上引入前体。之后，该方法氧化前体，加热前体，并以避免前体结晶的速率冷却前体。

73. 发明授权

US06524908B2 Method for forming refractory metal-silicon-nitrogen capacitors and structures formed 失效
$Method for forming refractory metal-silicon-nitrogen capacitors and structures formed$
标题翻译：形成难熔金属 - 硅 - 氮电容器和结构的方法
公开(公告)号：US06524908B2
公开(公告)日：2003-02-25
申请号：US09872603
申请日：2001-06-01
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
IPC分类号： H01L218242
CPC分类号： H01L28/75 , C23C14/0073 , C23C14/0641 , H01L21/2855 , H01L21/28568
摘要： A method forforming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.
摘要翻译：描述了一种在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。在该方法中，首先将预处理的半导体衬底定位在溅射室中。然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

74. 发明授权

US07329600B2 Low dielectric semiconductor device and process for fabricating the same 失效
标题翻译：低介电半导体器件及其制造方法
公开(公告)号：US07329600B2
公开(公告)日：2008-02-12
申请号：US10817179
申请日：2004-04-02
申请人： Lawrence Clevenger , Louis Hsu , Christy S. Tyberg , Tsorng-Dih Yuan
发明人： Lawrence Clevenger , Louis Hsu , Christy S. Tyberg , Tsorng-Dih Yuan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.
摘要翻译：一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

75. 发明授权

US06831369B2 Semiconductor structure having in-situ formed unit resistors and method for fabrication 有权
标题翻译：具有原位形成单元电阻器的半导体结构和制造方法
公开(公告)号：US06831369B2
公开(公告)日：2004-12-14
申请号：US10705115
申请日：2003-11-10
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
摘要翻译：公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

76. 发明授权

US06707097B2 Method for forming refractory metal-silicon-nitrogen capacitors and structures formed 有权
$Method for forming refractory metal-silicon-nitrogen capacitors and structures formed$
标题翻译：形成难熔金属 - 硅 - 氮电容器和结构的方法
公开(公告)号：US06707097B2
公开(公告)日：2004-03-16
申请号：US10346437
申请日：2003-01-16
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Hsu , Keith Kwong Hon Wong
IPC分类号： H01L218242
CPC分类号： H01L28/75 , C23C14/0073 , C23C14/0641 , H01L21/2855 , H01L21/28568
摘要： A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.
摘要翻译：描述了在半导体结构中形成难熔金属 - 硅 - 氮电容器的方法和形成的结构。在该方法中，首先将预处理的半导体衬底定位在溅射室中。然后将Ar气体流入溅射室，以从耐火金属硅化物靶或从难熔金属和硅的两个靶溅射沉积在衬底上的第一难熔金属 - 硅 - 氮层。然后将N 2气体流入溅射室，直到室内的N 2气体的浓度至少为35％，以在第一难熔金属 - 硅 - 氮层的顶部溅射沉积第二难熔金属 - 硅 - 氮层。然后停止N 2气流以在第二难熔金属 - 硅 - 氮层的顶部溅射沉积第三难熔金属 - 硅 - 氮层。然后将难熔金属硅 - 氮的多层堆叠光刻形成电容器。

77. 发明授权

US06545339B2 Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication 失效
$Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication$
公开(公告)号：US06545339B2
公开(公告)日：2003-04-08
申请号：US09760245
申请日：2001-01-12
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L27108
CPC分类号： H01L21/76849 , H01L21/7687 , H01L21/76888 , H01L23/5258 , H01L27/0629 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

78. 发明申请

US20060270098A1 Method to fabricate passive components using conductive polymer 审中-公开
公开(公告)号：US20060270098A1
公开(公告)日：2006-11-30
申请号：US11499364
申请日：2006-08-04
申请人： Lawrence Clevenger , Louis Hsu , Carl Radens , Li-Kong Wang , Kwong Wong
发明人： Lawrence Clevenger , Louis Hsu , Carl Radens , Li-Kong Wang , Kwong Wong
IPC分类号： H01L21/00 , H01L21/20 , H01L21/30
CPC分类号： H01C7/005 , H01C7/006 , H01C17/075 , H01G4/18 , H01G4/33 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L23/5328 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for an integrated circuit chip has a logic core which includes a plurality of insulating and conducting levels, an exterior conductor level and passive devices having a conductive polymer directly connected to the exterior conductor level. The passive devices contain RF devices which also includes resistor, capacitor, and/or inductor. The resistors can be serpentine resistors and the capacitors can be interdigitated capacitors.

79. 发明申请

US20060024961A1 INTERLEVEL DIELECTRIC LAYER AND METAL LAYER SEALING 有权
标题翻译： INTERLEVEL介电层和金属层密封
公开(公告)号：US20060024961A1
公开(公告)日：2006-02-02
申请号：US10710706
申请日：2004-07-29
申请人： Matthew Angyal , Peter Biolsi , Lawrence Clevenger , Habib Hichri , Bernd Kastenmeier , Michael Lane , Jeffrey Marino , Vincent McGahay , Theodorus Standaert
发明人： Matthew Angyal , Peter Biolsi , Lawrence Clevenger , Habib Hichri , Bernd Kastenmeier , Michael Lane , Jeffrey Marino , Vincent McGahay , Theodorus Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76838 , H01L21/76844
摘要： Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.
摘要翻译：在蚀刻步骤之后密封有机ILD层和金属层的方法。该方法包括蚀刻穿过ILD层并留下下面的金属层帽的剩余部分，将该装置保持在惰性气体中，并将衬垫的至少一部分沉积到开口中以密封ILD层和金属层。随后的处理可以包括通过蚀刻穿过衬套的一部分和盖层的剩余部分以及沉积金属来形成通孔。

80. 发明申请

US20050227480A1 Low dielectric semiconductor device and process for fabricating the same 失效
标题翻译：低介电半导体器件及其制造方法
公开(公告)号：US20050227480A1
公开(公告)日：2005-10-13
申请号：US10817179
申请日：2004-04-02
申请人： Lawrence Clevenger , Louis Hsu , Christy Tyberg , Tsorng-Dih Yuan
发明人： Lawrence Clevenger , Louis Hsu , Christy Tyberg , Tsorng-Dih Yuan
IPC分类号： H01L21/31 , H01L21/4763 , H01L21/768 , H01L23/52 , H01L23/522 , H01L23/532
CPC分类号： H01L23/5222 , H01L21/76829 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A process for fabricating a low dielectric constant semiconductor comprising the steps of: depositing a first metal layer on a substrate; patterning the first metal layer to produce a patterned first metal wiring; applying a first insulating material onto the patterned first metal wiring to form a support structure; patterning the first insulating material by a contact printing process; depositing a second insulating material of lower dielectric constant onto the support structure; planarizing the second insulating material; depositing a polish-stop film layer over the planarized second insulating material, thereby forming a plurality of metal studs; depositing a second metal layer onto the polish-stop film layer forming interconnects with said studs; and patterning the metal layer to produce a second metal wiring interconnecting to the first wiring via the metal studs.
摘要翻译：一种制造低介电常数半导体的方法，包括以下步骤：在衬底上沉积第一金属层; 图案化第一金属层以产生图案化的第一金属布线; 将第一绝缘材料施加到所述图案化的第一金属布线上以形成支撑结构; 通过接触印刷方法图案化第一绝缘材料; 将较低介电常数的第二绝缘材料沉积到所述支撑结构上; 平面化第二绝缘材料; 在平坦化的第二绝缘材料上沉积抛光停止膜层，从而形成多个金属螺柱; 将第二金属层沉积到所述抛光 - 停止膜层上，形成与所述螺柱的互连; 以及图案化所述金属层以产生经由所述金属螺柱与所述第一布线互连的第二金属布线。

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