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1. 发明授权

US06700203B1 Semiconductor structure having in-situ formed unit resistors 有权
标题翻译：具有原位形成单元电阻器的半导体结构
公开(公告)号：US06700203B1
公开(公告)日：2004-03-02
申请号：US09686742
申请日：2000-10-11
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
摘要翻译：公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

2. 发明授权

US06828232B2 Semiconductor structure having in-situ formed unit resistors and method for fabrication 失效
公开(公告)号：US06828232B2
公开(公告)日：2004-12-07
申请号：US10705116
申请日：2003-11-10
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L214763
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

3. 发明授权

US06831369B2 Semiconductor structure having in-situ formed unit resistors and method for fabrication 有权
标题翻译：具有原位形成单元电阻器的半导体结构和制造方法
公开(公告)号：US06831369B2
公开(公告)日：2004-12-14
申请号：US10705115
申请日：2003-11-10
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2348
CPC分类号： H01L28/20 , H01L27/0688
摘要： An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.
摘要翻译：公开了一种具有原位形成的单位电阻器的电子结构及其制造方法。具有原位形成的单元电阻器的电子结构由形成在绝缘材料层中的第一多个导电元件组成，多个电阻通孔形成在顶部并与第一多个导电元件中的至少一个电连通以及形成在所述多个电阻通孔中的至少一个上方并与之电气连通的第二多个导电元件。本发明的新颖结构可以进一步形成为多电平配置，使得多电平电阻器可以串联连接以提供更大的电阻值。本发明的新颖结构还可以与电容器网络组合以形成期望的RC电路。

4. 发明授权

US06545339B2 Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication 失效
$Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication$
公开(公告)号：US06545339B2
公开(公告)日：2003-04-08
申请号：US09760245
申请日：2001-01-12
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L27108
CPC分类号： H01L21/76849 , H01L21/7687 , H01L21/76888 , H01L23/5258 , H01L27/0629 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

5. 发明授权

US06794226B2 Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication 有权
$Semiconductor device incorporating elements formed of refractory metal-silicon-nitrogen and method for fabrication$
标题翻译：掺入由难熔金属硅 - 氮形成的元件的半导体器件及其制造方法
公开(公告)号：US06794226B2
公开(公告)日：2004-09-21
申请号：US10374395
申请日：2003-02-26
申请人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
发明人： Cyril Cabral, Jr. , Lawrence Clevenger , Louis Lu-Chen Hsu , Keith Kwong Hon Wong
IPC分类号： H01L2182
CPC分类号： H01L21/76849 , H01L21/7687 , H01L21/76888 , H01L23/5258 , H01L27/0629 , H01L28/24 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.
摘要翻译：公开了一种半导体结构，其包括由难熔金属 - 硅 - 氮形成的熔丝，扩散阻挡层或电容器的至少一个电路元件。还公开了一种通过难熔金属硅 - 氮材料制造这种半导体结构的方法，其包括熔丝元件，扩散阻挡层，电阻器或电容器。要使用的合适的难熔金属 - 硅 - 氮材料是TaSiN，其通过改变Ta:Si:N的比例来提供宽范围的电阻率。本发明提供了通过TaSiN层的单个沉积工艺可以形成扩散阻挡层，保险丝，电容器和电阻器的各种组件的优点，然后通过热处理或离子注入对各种组分进行选择性掩蔽和处理，选择性地改变其电阻率，同时保持其他屏蔽元件具有相同的电阻率。

6. 发明授权

US06426903B1 Redundancy arrangement using a focused ion beam 有权
标题翻译：使用聚焦离子束进行冗余布置
公开(公告)号：US06426903B1
公开(公告)日：2002-07-30
申请号：US09923721
申请日：2001-08-07
申请人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Li-Kong Wang , Keith Kwong-Hon Wong
发明人： Lawrence A. Clevenger , Louis Lu-Chen Hsu , Li-Kong Wang , Keith Kwong-Hon Wong
IPC分类号： G11C700
CPC分类号： G11C29/80 , Y10S977/888 , Y10S977/943
摘要： A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.
摘要翻译：使用聚焦离子束反熔丝方法的电路的静态冗余布置，与现有技术的动态冗余方案相比，其减小了电路布局面积和开关活动，导致较少的功率，更简单的设计和更高的速度。聚焦离子束反熔丝方法用于编程电路冗余，特别是宽I / O嵌入式DRAM宏。反熔丝阵列电路由多个反熔丝编程元件组成，每个反熔丝编程元件包括由设定的输入信号控制的锁存电路和由聚焦离子束编程的反熔丝器件。

7. 发明申请

US20120248567A1 LAYERED STRUCTURE WITH FUSE 有权
标题翻译：带保险丝的层状结构
公开(公告)号：US20120248567A1
公开(公告)日：2012-10-04
申请号：US13494327
申请日：2012-06-12
申请人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
发明人： Louis Lu-Chen Hsu , Jack Allan Mandelman , William Robert Tonti , Chih-Chao Yang
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate, a first electrode in the substrate, first dielectric layer above both the substrate and the first electrode, a second dielectric layer above the first dielectric layer, and a fuse element buried in the first dielectric layer. The first electrode includes a first electrically conductive material. A top surface of the first dielectric layer is further from a top surface of the first electrode than is any other surface of the first dielectric layer. The first dielectric layer includes a first dielectric material and a second dielectric material. A bottom surface of the second dielectric layer is in direct physical contact with the top surface of the first dielectric layer. The second dielectric layer includes the second dielectric material.
摘要翻译：一个结构。该结构包括：衬底，衬底中的第一电极，衬底和第一电极上的第一电介质层，第一电介质层上方的第二电介质层和埋在第一电介质层中的熔丝元件。第一电极包括第一导电材料。第一电介质层的顶表面比第一电介质层的任何其它表面更远离第一电极的顶表面。第一电介质层包括第一电介质材料和第二电介质材料。第二电介质层的底表面与第一电介质层的顶表面直接物理接触。第二电介质层包括第二电介质材料。

8. 发明授权

US07984408B2 Structures incorporating semiconductor device structures with reduced junction capacitance and drain induced barrier lowering 有权
标题翻译：结合了具有减小的结电容和漏极引起的屏障降低的半导体器件结构
公开(公告)号：US07984408B2
公开(公告)日：2011-07-19
申请号：US11875013
申请日：2007-10-19
申请人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman , Haining Yang
发明人： Kangguo Cheng , Louis Lu-Chen Hsu , Jack Allan Mandelman , Haining Yang
IPC分类号： G06F17/50 , H01L29/76
CPC分类号： H01L29/78603 , G11C29/54 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/66636 , H01L29/66772
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes semiconductor device structures characterized by reduced junction capacitance and drain induced barrier lowering. The semiconductor device structure of the design structure includes a semiconductor layer and a dielectric layer disposed between the semiconductor layer and the substrate. The dielectric layer includes a first dielectric region with a first dielectric constant and a second dielectric region with a second dielectric constant that is greater than the first dielectric constant.
摘要翻译：用于设计，制造或测试设计的机器可读介质中体现的设计结构。该设计结构包括半导体器件结构，其特征在于结电容减小和漏极引起的栅极降低。设计结构的半导体器件结构包括设置在半导体层和衬底之间的半导体层和介电层。电介质层包括具有第一介电常数的第一电介质区域和具有大于第一介电常数的第二介电常数的第二电介质区域。

9. 发明授权

US07968949B2 Contact forming method and related semiconductor device 有权
标题翻译：接触形成方法及相关半导体器件
公开(公告)号：US07968949B2
公开(公告)日：2011-06-28
申请号：US11668717
申请日：2007-01-30
申请人： Daniel C. Edelstein , Louis Lu-Chen Hsu , Chih-Chao Yang
发明人： Daniel C. Edelstein , Louis Lu-Chen Hsu , Chih-Chao Yang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76829 , H01L21/76831 , H01L29/6653 , H01L29/78
摘要： Contact forming methods and a related semiconductor device are disclosed. One method includes forming a first liner over the structure and the substrate, the first liner covering sidewall of the structure; forming a dielectric layer over the first liner and the structure; forming a contact hole in the dielectric layer to the first liner; forming a second liner in the contact hole including over the first liner covering the sidewall; removing the first and second liners at a bottom of the contact hole; and filling the contact hole with a conductive material to form the contact. The thicker liner(s) over the sidewall of the structure prevents shorting, and allows for at least maintaining any intrinsic stress in one or more of the liner(s).
摘要翻译：公开了触点形成方法和相关的半导体器件。一种方法包括在结构和衬底上形成第一衬里，第一衬套覆盖结构的侧壁; 在所述第一衬垫和所述结构上形成介电层; 在所述介电层中形成与所述第一衬垫的接触孔; 在所述接触孔中形成第二衬垫，包括覆盖所述侧壁的所述第一衬套上方; 在接触孔的底部移除第一和第二衬垫; 并用导电材料填充接触孔以形成接触。结构侧壁上较厚的衬套防止短路，并允许至少保持一个或多个衬套中的任何固有应力。

10. 发明授权

US07833873B2 Method and structure to reduce contact resistance on thin silicon-on-insulator device 有权
公开(公告)号：US07833873B2
公开(公告)日：2010-11-16
申请号：US12174683
申请日：2008-07-17
申请人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
发明人： Brian J. Greene , Louis Lu-Chen Hsu , Jack Allan Mandelman , Chun-Yung Sung
IPC分类号： H01L21/76
CPC分类号： H01L29/458 , H01L29/66628 , H01L29/66772
摘要： A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

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