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71. 发明授权

US07483329B2 Flash card and controller with integrated voltage converter for attachment to a bus that can operate at either of two power-supply voltages 失效
标题翻译：闪存卡和具有集成电压转换器的控制器，用于连接到可在两个电源电压中任一个工作的总线
公开(公告)号：US07483329B2
公开(公告)日：2009-01-27
申请号：US11625309
申请日：2007-01-20
申请人： Jianjun Luo , Chris Tsu , Charles C. Lee , Ming-Shiang Shen
发明人： Jianjun Luo , Chris Tsu , Charles C. Lee , Ming-Shiang Shen
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C5/147 , G11C16/30
摘要： A dual-voltage secure digital (SD) card can be inserted into a legacy host or a newer host. Legacy hosts drive a high voltage such as 3.3 volts onto the power line of the SD bus, while newer hosts drive the power line with a reduced voltage such as 1.8 volts. A flash and voltage controller chip on the SD card has a controller core that operates at the reduced voltage. A voltage regulator on the SD card, or a power management unit inside the controller chip generates an internal power voltage of 1.8 volts from the dual-voltage SD bus power line. The internal power voltage is applied to the controller core and to a voltage converter that generates a flash power voltage from the internal power voltage. The flash power voltage is applied to flash-memory chips on the SD card that operate at the higher voltage.
摘要翻译：可以将双电压安全数字（SD）卡插入到旧式主机或更新的主机中。传统主机将高压（例如3.3伏特）驱动到SD总线的电源线上，而较新的主机则以1.8伏特的降低电压驱动电源线。 SD卡上的闪存和电压控制器芯片具有以降低的电压工作的控制器核心。 SD卡上的电压调节器或控制器芯片内的电源管理单元从双电压SD总线电源线产生1.8伏特的内部电源电压。内部电源电压被施加到控制器核心和电压转换器，其从内部电源电压产生闪光电源电压。闪存电源电压被施加到在更高电压下工作的SD卡上的闪存芯片。

72. 发明授权

US08061905B2 Multi-level cell (MLC) dual personality extended fiber optic flash memory device 失效
标题翻译：多级单元（MLC）双重人格扩展光纤闪存设备
公开(公告)号：US08061905B2
公开(公告)日：2011-11-22
申请号：US12111872
申请日：2008-04-29
申请人： Abraham Ma , I-Kang Yu , David Nguyen , Charles C. Lee , Ming-Shiang Shen
发明人： Abraham Ma , I-Kang Yu , David Nguyen , Charles C. Lee , Ming-Shiang Shen
IPC分类号： G02B6/38
CPC分类号： G06K19/07732
摘要： A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data.
摘要翻译：多级单元（MLC）双人格扩展光纤闪存驱动器包括连接到双人格扩展光纤闪存驱动器的MLC双人格扩展光纤通用串行总线（USB）插头连接器，并且可移除地连接到主办。该连接器适用于接收电气数据和光学数据。位于闪存驱动器上的收发器用于将接收的电数据转换为光学数据或将接收到的光学数据转换为电气数据。

73. 发明授权

US07886108B2 Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device 失效
标题翻译：在基于大容量多级单元（MLC）的闪存设备中管理存储器地址的方法和系统
公开(公告)号：US07886108B2
公开(公告)日：2011-02-08
申请号：US12025706
申请日：2008-02-04
申请人： Charles C. Lee , I-Kang Yu , David Nguyen , Abraham Chih-Kang Ma , Ming-Shiang Shen
发明人： Charles C. Lee , I-Kang Yu , David Nguyen , Abraham Chih-Kang Ma , Ming-Shiang Shen
IPC分类号： G06F13/16
CPC分类号： G06F12/0246 , G06F12/0607 , G11C11/5621 , G11C16/0408 , G11C16/349 , G11C16/3495
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译：描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。闪存被分为N组。每个集合包括多个条目（即，块）。对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

74. 发明申请

US20080318449A1 MULTI-LEVEL CELL (MLC) DUAL PERSONALITY EXTENDED eSATA FLASH MEMORY DEVICE 审中-公开
标题翻译：多级电池（MLC）双人个性扩展eSATA闪存存储器件
公开(公告)号：US20080318449A1
公开(公告)日：2008-12-25
申请号：US12113023
申请日：2008-04-30
申请人： Abraham Ma , I-Kang Yu , David Nguyen , Charles C. Lee , Ming-Shiang Shen
发明人： Abraham Ma , I-Kang Yu , David Nguyen , Charles C. Lee , Ming-Shiang Shen
IPC分类号： H01R24/00 , H01R12/00 , G06K9/00
CPC分类号： H01R29/00
摘要： A multi-level cell (MLC) dual-personality extended External Serial Advanced Technology Attachment (eSATA) flash drive includes a MLC dual-personality extended eSATA plug connector connected to a flash drive and removably connectable to a host. The connector is adaptable to receive electoral data from both a USB and eSATA interface.
摘要翻译：多级单元（MLC）双人格扩展外部串行高级技术附件（eSATA）闪存驱动器包括连接到闪存驱动器并可拆卸地连接到主机的MLC双人格扩展eSATA插头连接器。该连接器适用于从USB和eSATA接口接收选举数据。

75. 发明申请

US20080256287A1 Methods and systems of managing memory addresses in a large capacity multi-level cell (MLC) based flash memory device 失效
标题翻译：在基于大容量多级单元（MLC）的闪存设备中管理存储器地址的方法和系统
公开(公告)号：US20080256287A1
公开(公告)日：2008-10-16
申请号：US12025706
申请日：2008-02-04
申请人： Charles C. Lee , I-Kang Yu , David Nguyen , Abraham Chih-Kang Ma , Ming-Shiang Shen
发明人： Charles C. Lee , I-Kang Yu , David Nguyen , Abraham Chih-Kang Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0607 , G11C11/5621 , G11C16/0408 , G11C16/349 , G11C16/3495
摘要： Methods and systems of managing memory addresses in a large capacity multi-level cell based flash memory device are described. According to one aspect, a flash memory device comprises a processing unit to manage logical-to-physical address correlation using an indexing scheme. The flash memory is partitioned into N sets. Each set includes a plurality of entries (i.e., blocks). N sets of partial logical entry number to physical block number and associated page usage information (hereinafter ‘PLTPPUI’) are stored in the reserved area of the MLC based flash memory. Only one the N sets is loaded to address correlation and page usage memory (ACPUM), which is a limited size random access memory (RAM). In one embodiment, static RAM (SRAM) is implemented for fast access time for the address correlation. LSA received together with the data transfer request dictates which one of the N sets of PLTPPUI is loaded into ACPUM.
摘要翻译：描述了在大容量多级基于单元的闪存设备中管理存储器地址的方法和系统。根据一个方面，一种闪存设备包括一个使用索引方案来管理逻辑到物理地址相关的处理单元。闪存被分为N组。每个集合包括多个条目（即，块）。对于物理块号和相关联的页面使用信息（以下称为“PLTPPUI”）的N组部分逻辑条目号被存储在基于MLC的闪速存储器的保留区域中。只有一个N集被加载以寻址相关和页面使用存储器（ACPUM），这是一个有限大小的随机存取存储器（RAM）。在一个实施例中，静态RAM（SRAM）被实现用于地址相关的快速访问时间。与数据传输请求一起接收的LSA指示将N组PLTPPUI中的哪一个加载到ACPUM中。

76. 发明申请

US20080209112A1 High Endurance Non-Volatile Memory Devices 有权
标题翻译：高耐久性非易失性存储器件
公开(公告)号：US20080209112A1
公开(公告)日：2008-08-28
申请号：US12035398
申请日：2008-02-21
申请人： I-Kang Yu , David Q. Chow , Charles C. Lee , Abraham Chih-Kang Ma , Ming-Shiang Shen
发明人： I-Kang Yu , David Q. Chow , Charles C. Lee , Abraham Chih-Kang Ma , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F12/0246 , G06F12/0862 , G06F12/123 , G06F2212/7203 , G11C11/5621 , G11C11/5678 , G11C13/0004 , G11C2211/5641 , G11C2211/5643
摘要： High endurance non-volatile memory devices (NVMD) are described. A high endurance NVMD includes an I/O interface, a NVM controller, a CPU along with a volatile memory subsystem and at least one non-volatile memory (NVM) module. The volatile memory cache subsystem is configured as a data cache subsystem. The at least one NVM module is configured as a data storage when the NVMD is adapted to a host computer system. The I/O interface is configured to receive incoming data from the host to the data cache subsystem and to send request data from the data cache subsystem to the host. The at least one NVM module may comprise at least first and second types of NVM. The first type comprises SLC flash memory while the second type MLC flash. The first type of NVM is configured as a buffer between the data cache subsystem and the second type of NVM.
摘要翻译：描述了高耐久性非易失性存储器件（NVMD）。高耐久性NVMD包括I / O接口，NVM控制器，CPU以及易失性存储器子系统和至少一个非易失性存储器（NVM）模块。易失性存储器缓存子系统被配置为数据高速缓存子系统。当NVMD适用于主机系统时，至少一个NVM模块被配置为数据存储器。 I / O接口被配置为从主机接收数据缓存子系统的传入数据，并将请求数据从数据缓存子系统发送到主机。至少一个NVM模块可以包括至少第一和第二类型的NVM。第一种类型包括SLC闪存，而第二种类型的MLC闪存。 NVM的第一种类型被配置为数据高速缓存子系统和第二类NVM之间的缓冲区。

77. 发明授权

US08200862B2 Low-power USB flash card reader using bulk-pipe streaming with UAS command re-ordering and channel separation 失效
标题翻译：低功耗USB闪存卡阅读器，采用UAS命令重新排序和通道分离的大容量流式传输
公开(公告)号：US08200862B2
公开(公告)日：2012-06-12
申请号：US12887477
申请日：2010-09-21
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F13/12 , G06F13/00 , G06F12/02
CPC分类号： G06F13/28 , G11C13/0004 , G11C16/102 , G11C2216/30 , Y02D10/14
摘要： A flash-card reader improves transmission efficiency by using bulk streaming of multiple pipes. A bulk data-out pipe carries host write data to the card reader and can operate in parallel with a bulk data-in pipe that carries host read data that was read from a flash card attached to the card reader. Status packets do not block data packets since the he status packets are buffered through a separate status pipe, and commands are buffered through a command pipe. Flash data from multiple flash cards are interleaved as separate endpoints that share the bulk data-in pipe. A data in/out streaming state machine controls streaming bulk data through the bulk data-in and data-out pipes, while a status streaming state machine controls streaming status packets through the status pipe. Transaction overhead is reduced using bulk streaming where packets for several commands are combined into the same bulk streams.
摘要翻译：闪存卡读卡器通过使用多个管道的批量流传输来提高传输效率。批量数据输出管道将主机写入数据传送到读卡器，并且可以与承载从附接到读卡器的闪存卡读取的主机读取数据的批量数据输入管并行操作。状态数据包不会阻塞数据包，因为状态数据包通过单独的状态管道进行缓冲，命令通过命令管道缓冲。来自多个闪存卡的闪存数据被交织为共享大容量数据管道的单独端点。数据输入/输出流状态机通过批量数据输入和数据输出管道控制流批量数据，而状态流状态机通过状态管道控制流状态数据包。使用批量流量减少事务开销，其中几个命令的数据包被组合成相同的批量流。

78. 发明申请

US20110213921A1 Command Queuing Smart Storage Transfer Manager for Striping Data to Raw-NAND Flash Modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据传送到原始NAND闪存模块
公开(公告)号：US20110213921A1
公开(公告)日：2011-09-01
申请号：US13104257
申请日：2011-05-10
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0607 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

79. 发明申请

US20100122021A1 USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch 失效
标题翻译： USB附加SCSI闪存系统，带有附加命令，状态和控制管道到智能存储交换机
公开(公告)号：US20100122021A1
公开(公告)日：2010-05-13
申请号：US12651334
申请日：2009-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00 , G06F12/02 , G06F13/00
CPC分类号： G06F3/0661 , G06F3/0613 , G06F3/0688 , G11C11/5678 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.
摘要翻译：电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

80. 发明申请

US20100023682A1 Flash-Memory System with Enhanced Smart-Storage Switch and Packed Meta-Data Cache for Mitigating Write Amplification by Delaying and Merging Writes until a Host Read 有权
标题翻译：具有增强型智能存储交换机和封装元数据缓存的闪存系统，用于通过延迟和合并写入来缓解写入放大，直到主机读取
公开(公告)号：US20100023682A1
公开(公告)日：2010-01-28
申请号：US12576216
申请日：2009-10-08
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/1036 , G06F2212/214 , G06F2212/7203 , G06F2212/7207 , G11C13/0004 , G11C16/102 , G11C19/0808 , G11C2211/5641 , G11C2216/30
摘要： A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
摘要翻译：闪存固态驱动器（SSD）具有智能存储交换机，可以减少写入快速写入的速度，而写入速度会比从主机接收到的更多的数据写入闪存。页面映射而不是块映射减少写入加速。主机命令加载到逻辑块地址（LBA）范围FIFO中。当新命令与FIFO中的旧命令重叠时，条目被分割，部分无效。主机数据与页边界对齐，前后获取的数据填充到边界。通过存储在元模式闪存块的元模式高速缓存中的元模式条目中的压缩元数据代码来检测和编码重复的数据模式。扇区数据未写入闪存。使用元数据映射表定位元模式条目。存储主机CRC用于与传入主机数据进行比较可以检测可跳过的相同数据写入，避免写入闪存。

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