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1. 发明授权

US07680977B2 Page and block management algorithm for NAND flash 有权
标题翻译： NAND闪存的页面和块管理算法
公开(公告)号：US07680977B2
公开(公告)日：2010-03-16
申请号：US11779804
申请日：2007-07-18
申请人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
发明人： Jianjun Luo , Chris Tsu , Charles Chung Lee , David Queichang Chow
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0292 , G06F13/28 , G06F2212/1036 , G06F2212/7211
摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
摘要翻译：闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。逻辑地址由控制器用于识别块。该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加，指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与最大数量的另一组块的属性值。

2. 发明申请

US20090300259A1 SSD WITH SATA AND USB INTERFACES 有权
标题翻译： SSD与SATA和USB接口
公开(公告)号：US20090300259A1
公开(公告)日：2009-12-03
申请号：US12468786
申请日：2009-05-19
申请人： Jianjun LUO , ChuanJen TSU , Minhorng KO
发明人： Jianjun LUO , ChuanJen TSU , Minhorng KO
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/385
摘要： In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.
摘要翻译：在一个实施例中，数据存储系统包括控制器和多个固态存储器件，每个固态存储器件包括至少一个存储器单元。控制器包括第一类型的数据接口，第二类型的数据接口和第一串行数据总线。第一类型和第二类型的每个数据接口被配置为耦合到主机设备的相应数据接口。第一串行数据总线耦合到第一类型和第二类型的数据接口以及多个固态存储器件。所述控制器被配置为通过所述第一类型和第二类型的数据接口来管理所述多个固态存储设备与所述主机设备之间的数据流。

3. 发明申请

US20090300258A1 SSD WITH A CHANNEL MULTIPLIER 有权
标题翻译：带通道乘法器的SSD
公开(公告)号：US20090300258A1
公开(公告)日：2009-12-03
申请号：US12468683
申请日：2009-05-19
申请人： Jianjun LUO , ChuanJen TSU , Jui Chuan LIANG , Minhorng KO
发明人： Jianjun LUO , ChuanJen TSU , Jui Chuan LIANG , Minhorng KO
IPC分类号： G06F13/20 , G06F12/02
CPC分类号： G06F13/1684 , G06F3/0613 , G06F3/0658 , G06F3/0688
摘要： An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.
摘要翻译：集成电路包括第一串行高级技术附件（SATA）通道，多个第二SATA通道和通道倍增器。第一SATA通道被配置为耦合到主机设备的相应串行数据总线。多个SATA通道中的每一个被配置为耦合到相应的单独的存储器件通道。信道乘法器被配置为将第一SATA信道耦合到多个第二SATA信道中的每一个。

4. 发明申请

US20070276988A1 Page and Block Management Algorithm for NAND Flash 有权
标题翻译： NAND Flash的页面和块管理算法
公开(公告)号：US20070276988A1
公开(公告)日：2007-11-29
申请号：US11779804
申请日：2007-07-18
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G06F13/28
CPC分类号： G06F12/0246 , G06F12/0292 , G06F13/28 , G06F2212/1036 , G06F2212/7211
摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
摘要翻译：闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。逻辑地址由控制器用于识别块。该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加，指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与最大数量的另一组块的属性值。

5. 发明授权

US08244961B2 SSD with distributed processors 有权
标题翻译：带分布式处理器的SSD
公开(公告)号：US08244961B2
公开(公告)日：2012-08-14
申请号：US12468748
申请日：2009-05-19
申请人： Jianjun Luo , ChuanJen Tsu
发明人： Jianjun Luo , ChuanJen Tsu
IPC分类号： G06F12/08
CPC分类号： G06F12/0246 , G06F3/0611 , G06F3/0658 , G06F3/0688 , G06F11/1068 , G06F2212/7205 , G06F2212/7208 , G11C2211/5641
摘要： In one embodiment, a system includes a serial data bus, a plurality of processors of a first type, and a processor of a second type. The serial data bus is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of processors of the first type is coupled to a respective flash memory device. The processor of the second type is configured to manage the access that the plurality of the processors of the first type have to the serial data bus.
摘要翻译：在一个实施例中，系统包括串行数据总线，第一类型的多个处理器和第二类型的处理器。串行数据总线被配置为耦合到主机设备的相应串行数据总线。第一类型的多个处理器中的每一个耦合到相应的闪存器件。第二类型的处理器被配置为管理第一类型的多个处理器对串行数据总线的访问。

6. 发明授权

US07970978B2 SSD with SATA and USB interfaces 有权
标题翻译： SSD与SATA和USB接口
公开(公告)号：US07970978B2
公开(公告)日：2011-06-28
申请号：US12468786
申请日：2009-05-19
申请人： Jianjun Luo , ChuanJen Tsu , Minhorng Ko
发明人： Jianjun Luo , ChuanJen Tsu , Minhorng Ko
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/385
摘要： In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types.
摘要翻译：在一个实施例中，数据存储系统包括控制器和多个固态存储器件，每个固态存储器件包括至少一个存储器单元。控制器包括第一类型的数据接口，第二类型的数据接口和第一串行数据总线。第一类型和第二类型的每个数据接口被配置为耦合到主机设备的相应数据接口。第一串行数据总线耦合到第一类型和第二类型的数据接口以及多个固态存储器件。所述控制器被配置为通过所述第一类型和第二类型的数据接口来管理所述多个固态存储设备与所述主机设备之间的数据流。

7. 发明授权

US07895457B2 Memory card with power saving 有权
标题翻译：存储卡省电
公开(公告)号：US07895457B2
公开(公告)日：2011-02-22
申请号：US11841550
申请日：2007-08-20
申请人： Jianjun Luo , David Queichang Chow
发明人： Jianjun Luo , David Queichang Chow
IPC分类号： G06F1/00 , G06F1/32 , G06F12/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3275 , Y02D10/126 , Y02D10/14
摘要： A memory system includes power saving arbitrator responsive to a clock oscillator and having a first clock rate. The power saving arbitrator includes an active enable circuit responsive to a host clock and a host command and operative to generate an active enable signal for causing the power saving arbitrator to generate a core logic/memories signal having a second clock rate that is adjustably lower in rate than the first clock rate, said active enable circuit operative to detect the absence of a host command for a predetermined period of time and when the predetermined period of time exceeds a threshold value, the power saving arbitrator operative to reduce the second clock rate.
摘要翻译：存储器系统包括响应于时钟振荡器并具有第一时钟速率的节电仲裁器。省电仲裁器包括响应于主机时钟和主机命令的有效使能电路，并且可操作以产生有效使能信号，以使得省电仲裁器产生具有可调节地较低的第二时钟速率的核心逻辑/存储器信号所述有效使能电路可操作以在预定时间段内检测到主机命令的不存在，并且当所述预定时间段超过阈值时，所述节电仲裁器可操作地降低所述第二时钟速率。

8. 发明授权

US07600122B2 Methods and apparatus for accelerating secure session processing 失效
标题翻译：加速安全会话处理的方法和装置
公开(公告)号：US07600122B2
公开(公告)日：2009-10-06
申请号：US11593102
申请日：2006-11-06
申请人： Joseph Tardo , Mark Buer , Jianjun Luo , Don Matthews , Zheng Qi , Ronald Squires
发明人： Joseph Tardo , Mark Buer , Jianjun Luo , Don Matthews , Zheng Qi , Ronald Squires
IPC分类号： G06F9/00
CPC分类号： H04L9/0838
摘要： Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.
摘要翻译：为诸如CPU的实体提供方法和装置，以有效地调用加密加速器来执行加密操作。函数调用使密码加速器以针对特定处理步骤的方式执行多个加密操作，例如在安全会话的握手阶段期间的步骤。这些技术提供了硬件处理资源，数据接口和存储器接口的有效利用。

9. 发明申请

US20060085640A1 Methods and apparatus for accelerating secure session processing 有权
公开(公告)号：US20060085640A1
公开(公告)日：2006-04-20
申请号：US11286111
申请日：2005-11-23
申请人： Joseph Tardo , Mark Buer , Jianjun Luo , Don Matthews , Zheng Qi , Ronald Squires
发明人： Joseph Tardo , Mark Buer , Jianjun Luo , Don Matthews , Zheng Qi , Ronald Squires
IPC分类号： H04L9/00
CPC分类号： H04L9/0838
摘要： Methods and apparatus are provided for an entity such as a CPU to efficiently call a cryptography accelerator to perform cryptographic operations. A function call causes the cryptography accelerator to execute multiple cryptographic operations in a manner tailored for specific processing steps, such as steps during a handshake phase of a secured session. The techniques provide efficient use of hardware processing resources, data interfaces, and memory interfaces.

10. 发明授权

US08151038B2 SSD with a channel multiplier 有权
标题翻译： SSD带有通道倍增器
公开(公告)号：US08151038B2
公开(公告)日：2012-04-03
申请号：US12468683
申请日：2009-05-19
申请人： Jianjun Luo , ChuanJen Tsu , Jui Chuan Liang , Minhorng Ko
发明人： Jianjun Luo , ChuanJen Tsu , Jui Chuan Liang , Minhorng Ko
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G06F3/0613 , G06F3/0658 , G06F3/0688
摘要： An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels.
摘要翻译：集成电路包括第一串行高级技术附件（SATA）通道，多个第二SATA通道和通道倍增器。第一SATA通道被配置为耦合到主机设备的相应串行数据总线。多个SATA通道中的每一个被配置为耦合到相应的单独的存储器件通道。信道乘法器被配置为将第一SATA信道耦合到多个第二SATA信道中的每一个。

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