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1. 发明授权

US08452912B2 Flash-memory system with enhanced smart-storage switch and packed meta-data cache for mitigating write amplification by delaying and merging writes until a host read 有权
标题翻译：闪存系统具有增强的智能存储交换机和打包的元数据缓存，用于通过延迟和合并写入来缓解写入，直到主机读取
公开(公告)号：US08452912B2
公开(公告)日：2013-05-28
申请号：US12576216
申请日：2009-10-08
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0866 , G06F2212/1036 , G06F2212/214 , G06F2212/7203 , G06F2212/7207 , G11C13/0004 , G11C16/102 , G11C19/0808 , G11C2211/5641 , G11C2216/30
摘要： A flash memory solid-state-drive (SSD) has a smart storage switch that reduces write acceleration that occurs when more data is written to flash memory than is received from the host. Page mapping rather than block mapping reduces write acceleration. Host commands are loaded into a Logical-Block-Address (LBA) range FIFO. Entries are sub-divided and portions invalidated when a new command overlaps an older command in the FIFO. Host data is aligned to page boundaries with pre- and post-fetched data filling in to the boundaries. Repeated data patterns are detected and encoded by compressed meta-data codes that are stored in meta-pattern entries in a meta-pattern cache of a meta-pattern flash block. The sector data is not written to flash. The meta-pattern entries are located using a meta-data mapping table. Storing host CRC's for comparison to incoming host data can detect identical data writes that can be skipped, avoiding a write to flash.
摘要翻译：闪存固态驱动器（SSD）具有智能存储交换机，可以减少写入快速写入的速度，而写入速度会比从主机接收到的更多的数据写入闪存。页面映射而不是块映射减少写入加速。主机命令加载到逻辑块地址（LBA）范围FIFO中。当新命令与FIFO中的旧命令重叠时，条目被分割，部分无效。主机数据与页边界对齐，前后获取的数据填充到边界。通过存储在元模式闪存块的元模式高速缓存中的元模式条目中的压缩元数据代码来检测和编码重复的数据模式。扇区数据未写入闪存。使用元数据映射表定位元模式条目。存储主机CRC用于与传入主机数据进行比较可以检测可跳过的相同数据写入，避免写入闪存。

2. 发明授权

US08176238B2 Command queuing smart storage transfer manager for striping data to raw-NAND flash modules 有权
标题翻译：命令排队智能存储传输管理器，用于将数据分配到原始NAND闪存模块
公开(公告)号：US08176238B2
公开(公告)日：2012-05-08
申请号：US13104257
申请日：2011-05-10
申请人： Frank Yu , Charles C. Lee , Abraham C. Ma
发明人： Frank Yu , Charles C. Lee , Abraham C. Ma
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/0659 , G06F3/0688 , G06F12/0607 , G06F2212/7208 , G11C13/0004
摘要： A flash module has raw-NAND flash memory chips accessed over a physical-block address (PBA) bus by a NVM controller. The NVM controller is on the flash module or on a system board for a solid-state disk (SSD). The NVM controller converts logical block addresses (LBA) to physical block addresses (PBA). Data striping and interleaving among multiple channels of the flash modules is controlled at a high level by a smart storage transaction manager, while further interleaving and remapping within a channel may be performed by the NVM controllers. A SDRAM buffer is used by a smart storage switch to cache host data before writing to flash memory. A Q-R pointer table stores quotients and remainders of division of the host address. The remainder points to a location of the host data in the SDRAM. A command queue stores Q, R for host commands.
摘要翻译：闪存模块具有通过NVM控制器通过物理块地址（PBA）总线访问的原始NAND闪存芯片。 NVM控制器位于闪存模块或固态硬盘（SSD）的系统板上。 NVM控制器将逻辑块地址（LBA）转换为物理块地址（PBA）。闪存模块的多个通道之间的数据条带化和交织由智能存储事务管理器控制在高电平，而在信道内的进一步的交织和重新映射可由NVM控制器执行。智能存储交换机使用SDRAM缓冲区，在写入闪存之前缓存主机数据。 Q-R指针表存储主机地址的商和余数。剩余部分指向SDRAM中主机数据的位置。命令队列存储主机命令的Q，R。

3. 发明授权

US07707354B2 SRAM cache and flash micro-controller with differential packet interface 失效
标题翻译：具有差分数据包接口的SRAM缓存和闪存微控制器
公开(公告)号：US07707354B2
公开(公告)日：2010-04-27
申请号：US11876251
申请日：2007-10-22
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/2022 , G06F2212/2515
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The SRAM buffer also operates as a cache of flash data after booting is complete. Cache read and write hits use the SRAM cache rather than flash memory, while old cache lines and read misses access the flash memory. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory. The flash microcontroller uses a differential interface to the external host, with a differential transceiver and a differential serial interface. Frame, packet, and encoded clock processing is also performed by the serial interface.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导完成后，SRAM缓冲区还可以作为闪存数据缓存。缓存读取和写入命中使用SRAM缓存而不是闪存，而旧的缓存行和读取未命中访问闪存。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。闪存单片机使用与外部主机的差分接口，具有差分收发器和差分串行接口。帧，分组和编码时钟处理也由串行接口执行。

4. 发明申请

US20080320214A1 Multi-Level Controller with Smart Storage Transfer Manager for Interleaving Multiple Single-Chip Flash Memory Devices 有权
标题翻译：具有智能存储传输管理器的多级控制器，用于交错多个单片闪存器件
公开(公告)号：US20080320214A1
公开(公告)日：2008-12-25
申请号：US12186471
申请日：2008-08-05
申请人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
发明人： Abraham C. Ma , David Q. Chow , Charles C. Lee , Frank Yu
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/0613 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0664 , G06F3/0688 , G06F2212/7201 , G06F2212/7208 , G06F2212/7211 , G11C13/0004
摘要： A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.
摘要翻译：固态磁盘（SSD）具有智能存储交换机，智能存储交易管理器重新命令用于访问下游单芯片闪存设备的主机命令。每个单芯片闪存设备具有将逻辑块地址（LBA）转换为访问单芯片闪存设备中的闪存块的物理块地址（PBA）的较低级别的控制器。磨损均衡和坏块重映射由每个单芯片闪存设备执行，并且在智能存储交换机中的虚拟存储处理器处于更高级别。智能存储事务管理器和单芯片闪存设备之间的虚拟存储网桥将LBA总线上的LBA交易桥接到单芯片闪存设备。单芯片闪速存储器件的多个通道之间的数据条带化和交错由智能存储事务管理器控制在高电平，而可以在每个单芯片闪速存储器件内执行进一步的交错和重新映射。

5. 发明授权

US08180931B2 USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch 失效
标题翻译： USB连接的SCSI闪存系统，带有智能存储交换机的附加命令，状态和控制管道
公开(公告)号：US08180931B2
公开(公告)日：2012-05-15
申请号：US12651334
申请日：2009-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F3/0661 , G06F3/0613 , G06F3/0688 , G11C11/5678 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： An electronic flash-memory card has additional pipes for commands and status messages so that data pipes are not clogged with commands and status messages, allowing for a higher data throughput. The command and status pipes are activated when a UAS/BOT detector detects that a host is using a USB-Attached-SCSI (UAS) mode rather than a Bulk-Only-Transfer (BOT) mode. The host can send additional commands and data without waiting for completion of a prior command when operating in UAS mode but not while operating in BOT mode. A command queue (CQ) in the device re-orders commands for accessing flash memory and merges data in a RAM buffer. Smaller 1 KB USB packets in the data pipes are merged into larger 8 KB payloads in the RAM buffer, allowing for more efficient flash access.
摘要翻译：电子闪存卡具有用于命令和状态消息的附加管道，使得数据管道不被命令和状态消息阻塞，从而允许更高的数据吞吐量。当UAS / BOT检测器检测到主机正在使用USB-Attached-SCSI（UAS）模式而不是Bulk-Only-Transfer（BOT）模式时，命令和状态管道将被激活。主机可以发送附加的命令和数据，而不必在UAS模式下操作时等待先前的命令完成，而不能在BOT模式下运行。设备中的命令队列（CQ）重新命令用于访问闪存的命令，并将数据合并到RAM缓冲区中。数据管道中较小的1 KB USB数据包被合并到RAM缓冲区中的较大的8 KB有效载荷中，从而实现更高效的闪存访问。

6. 发明授权

US08171204B2 Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels 失效
标题翻译：智能固态非易失性存储器件（NVMD）系统具有多通道多级缓存
公开(公告)号：US08171204B2
公开(公告)日：2012-05-01
申请号：US12115128
申请日：2008-05-05
申请人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
发明人： David Q. Chow , Frank Yu , Charles C. Lee , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F13/00
CPC分类号： G06F12/1416 , G06F3/0664 , G06F12/0851 , G06F12/0866 , G06F12/0897 , G06F21/32 , G06F21/78 , G06F21/79 , G06F2212/2022 , Y02D10/13
摘要： A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.
摘要翻译：闪存系统存储由逻辑块地址（LBA）寻址的非易失性存储器件（NVMD）中的数据块。 NVBA将对LBA进行重新配置以进行磨损均衡和坏块重定位。 NVMD在由NVMD控制器访问的通道中进行交织。 NVMD控制器具有缓存存储在该通道中的NVMD中的块的控制器高速缓存，而NVMD还包含高速缓存。多级缓存可以减少访问延迟。电源由NVMD控制器中的电源控制器以多级管理，为NVMD内的电源管理器设置电源策略。闪存系统中的多个NVMD控制器可以各自控制多个NVMD通道。具有NVMD的闪存系统可能包括用于安全性的指纹读取器。

7. 发明授权

US08112574B2 Swappable sets of partial-mapping tables in a flash-memory system with a command queue for combining flash writes 有权
标题翻译：具有用于组合闪存写入的命令队列的闪存系统中的可转换的部分映射表
公开(公告)号：US08112574B2
公开(公告)日：2012-02-07
申请号：US12347306
申请日：2008-12-31
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma
IPC分类号： G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G11C16/102 , G11C2216/30
摘要： A flash controller has a flash interface accessing physical blocks of multi-level-cell (MLC) flash memory. An Extended Universal-Serial-Bus (EUSB) interface loads host commands into a command queue where writes are re-ordered and combined to reduce flash writes. A partial logical-to-physical L2P mapping table in a RAM has entries for only 1 of N sets of L2P mapping tables. The other N−1 sets are stored in flash memory and fetched into the RAM when a L2P table miss occurs. The RAM required for mapping is greatly reduced. A data buffer stores one page of host write data. Sector writes are merged using the data buffer. The data buffer is flushed to flash when a different page is written, while the partial logical-to-physical mapping table is flushed to flash when a L2P table miss occurs, when the host address is to a different one of the N sets of L2P mapping tables.
摘要翻译：闪存控制器具有访问多电平单元（MLC）闪存的物理块的闪存接口。扩展通用串行总线（EUSB）接口将主机命令加载到命令队列中，其中写入被重新排序并组合以减少闪存写入。 RAM中的部分逻辑到物理L2P映射表仅具有N组L2P映射表中的1个的条目。其他N-1组存储在闪存中，并在发生L2P表错误时被提取到RAM中。映射所需的RAM大大降低。数据缓冲器存储一页主机写入数据。扇区写入使用数据缓冲区进行合并。当写入不同的页面时，数据缓冲区被刷新闪存，而当L2P表错过发生时，部分逻辑到物理映射表被刷新为闪存，当主机地址是N组的L2P中的不同的一个映射表。

8. 发明授权

US07966462B2 Multi-channel flash module with plane-interleaved sequential ECC writes and background recycling to restricted-write flash chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收到限制写入闪存芯片
公开(公告)号：US07966462B2
公开(公告)日：2011-06-21
申请号：US11871627
申请日：2007-10-12
申请人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
发明人： Charles C. Lee , Frank Yu , Ming-Shiang Shen , Abraham C. Ma , David Q. Chow
IPC分类号： G06F12/02
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

9. 发明授权

US07761653B2 Flash micro-controller with shadow boot-loader SRAM for dual-device booting of micro-controller and host 失效
标题翻译：闪存微控制器带有引导加载器的SRAM，用于微控制器和主机的双设备启动
公开(公告)号：US07761653B2
公开(公告)日：2010-07-20
申请号：US11875648
申请日：2007-10-19
申请人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
发明人： Charles C. Lee , David Q. Chow , Abraham C. Ma , Frank Yu , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F9/441
摘要： A flash microcontroller has a Static Random-Access-Memory (SRAM) buffer that stores several blocks of boot code read from a flash memory. The boot code includes an initial boot loader, boot code and a control program that are executed by the flash microcontroller, and an operating system OS image and an external-host control program that are executed by an external host. Both the external host and the microcontroller are booted from boot code buffered in the SRAM buffer. A first-reset-read address from the external host is captured by the microcontroller during its boot sequence and stored in a mapping table along with a physical address of the block in the SRAM buffer with the operating system OS image and the external-host control program. A boot-loader state machine reads the flash ID and programs flash parameter registers with timing parameters for the flash memory.
摘要翻译：闪存微控制器具有静态随机存取存储器（SRAM）缓冲器，其存储从闪存读取的几个引导代码块。引导代码包括由闪存微控制器执行的初始引导加载程序，引导代码和控制程序，以及由外部主机执行的操作系统OS映像和外部主机控制程序。外部主机和微控制器均由缓冲在SRAM缓冲区中的引导代码引导。微控制器在其引导序列期间捕获来自外部主机的第一复位读取地址，并将其与SRAM缓冲器中具有操作系统OS映像和外部主机控制的块的物理地址一起存储在映射表中程序。引导加载器状态机读取闪存ID，并使用Flash存储器的时序参数对闪存参数寄存器进行编程。

10. 发明授权

US07620769B2 Recycling partially-stale flash blocks using a sliding window for multi-level-cell (MLC) flash memory 失效
标题翻译：使用多层单元（MLC）闪存的滑动窗口回收部分陈旧的闪存块
公开(公告)号：US07620769B2
公开(公告)日：2009-11-17
申请号：US11674645
申请日：2007-02-13
申请人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
发明人： Charles C. Lee , Frank Yu , Abraham C. Ma , Ming-Shiang Shen
IPC分类号： G06F12/02
CPC分类号： H01R13/629 , G06F12/0246 , G06F12/1416 , G06F21/32 , G06F21/78 , G06F2212/1044 , G06F2212/7201 , G06F2212/7205 , G06F2212/7209 , G06K9/00087 , G06K19/07 , G06K19/07354 , G07C9/00087
摘要： A sliding window of flash blocks is used to reduce wasted space occupied by stale data in a flash memory. The sliding window slides downward over a few flash blocks. The oldest block is examined for valid pages of data, and the valid pages are copied to the end of the sliding window so that the first block has only stale pages. The first block can then be erased and eventually re-used. A RAM usage table contains valid bits for pages in each block in the sliding window. A page's valid bit is changed from an erased, unwritten state to a valid state when data is written to the page. Later, when new host data replaces that data, the old page's valid bit is set to the stale state. A RAM stale-flags table keeps track of pages that are full of stale pages.
摘要翻译：闪存块的滑动窗口用于减少闪存中过时数据占用的浪费空间。滑动窗口向下滑过几个闪光块。检查最旧的块是否有效的数据页面，有效的页面被复制到滑动窗口的末尾，以便第一个块只有过时的页面。然后可以擦除第一个块并最终重新使用。 RAM使用表包含滑动窗口中每个块中页面的有效位。当数据写入页面时，页面的有效位从擦除的未写入状态更改为有效状态。之后，当新的主机数据替换该数据时，旧页面的有效位被设置为陈旧状态。 RAM陈旧标记表可以跟踪页面中已经有过时的页面。

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