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71. 发明授权

US5625591A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5625591A
公开(公告)日：1997-04-29
申请号：US445960
申请日：1995-05-22
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C29/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

72. 发明授权

US5095461A Erase circuitry for a non-volatile semiconductor memory device 失效
标题翻译：擦除非易失性半导体存储器件的电路
公开(公告)号：US5095461A
公开(公告)日：1992-03-10
申请号：US457859
申请日：1989-12-27
申请人： Tadashi Miyakawa , Masamichi Asano
发明人： Tadashi Miyakawa , Masamichi Asano
IPC分类号： G11C16/14
CPC分类号： G11C16/14
摘要： An memory cell array includes a plurality of electrically erasable and programmable memory cell transistors which are arranged in a matrix form and each of which includes a source region, drain region, floating gate, erasing gate and control gate. The patterns of the control gates and the source regions in the memory cell array are arranged in parallel along the row direction of the memory cell array and the patterns of the erasing gates are arranged to extend in the column direction of the memory cell array. The memory cell transistors in the memory cell array are selected by a row decoder and a column decoder. An erasing circuit functions to erase memory data of each memory cell transistor by applying an erasing potential to the erasing gate of the memory cell transistor. A source potential generation circuit applies a first potential for programming and readout to the source region of a memory cell transistor selected by the row and column decoders when data is programmed into or read out from the selected memory cell transistor and applies a second potential which is higher than the first potential and lower than the erasing potential to the source region of each memory cell transistor when memory data of each memory cell transistor is erased by the erasing circuit. A potential difference between the source region and the erasing gate of the memory cell transistor in the erasing mode is reduced by the second potential output from the source potential generation circuit.
摘要翻译：存储单元阵列包括以矩阵形式布置的多个电可擦除可编程存储单元晶体管，每个晶体管包括源区，漏区，浮置栅，擦除栅和控制栅。存储单元阵列中的控制栅极和源极区域的图案沿着存储单元阵列的行方向并排布置，并且擦除栅极的图案被布置成在存储单元阵列的列方向上延伸。存储单元阵列中的存储单元晶体管由行解码器和列解码器选择。擦除电路用于通过向存储单元晶体管的擦除栅极施加擦除电位来擦除每个存储单元晶体管的存储器数据。当数据被编程到所选择的存储单元晶体管中或从所选择的存储单元晶体管中读出时，源极电位产生电路将用于编程和读出的第一电位施加到由行和列解码器选择的存储单元晶体管的源极区域，并施加第二电位，当每个存储单元晶体管的存储器数据被擦除电路擦除时，高于第一电位并且低于每个存储单元晶体管的源极区的擦除电位。在擦除模式下存储单元晶体管的源极区域和擦除栅极之间的电位差由源极电位产生电路的第二个电位输出减小。

73. 发明授权

US5053841A Nonvolatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5053841A
公开(公告)日：1991-10-01
申请号：US423362
申请日：1989-10-18
申请人： Tadashi Miyakawa , Masamichi Asano , Tadayuki Taura , Atsushi Shoji , Michiharu Inami
发明人： Tadashi Miyakawa , Masamichi Asano , Tadayuki Taura , Atsushi Shoji , Michiharu Inami
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7886
摘要： A nonvolatile semiconductor memory includes a cell array in which electrically erasable programmable nonvolatile semiconductor memory cells, each using a cell transistor having source and drain regions in a semiconductor substrate, and a gate electrode with a three-layered structure on the semiconductor substrate are arranged in a matrix form. In the gate electrode having the three-layered structure, a first-layer floating gate electrode opposes a semiconductor substrate surface through a first gate insulating film, and a second- or third-layer gate electrode serves as one of erase and control gate electrodes. The erase gate electrode opposes a part of the floating gate electrode through a tunnel insulating film, and the control gate electrode opposes the floating gate electrode through a second gate insulating film. The erase and control gate electrodes are arranged to be parallel to each other, and to be perpendicular to the source and drain regions. Of two cell transistors adjacent to each other in a length direction of the channel region, the source region of one cell transistor is common to the drain region of the other cell transistor, and the cell transistors adjacent to each other in the widthwise direction of the channel region are element-isolated by an element isolation region formed in the semiconductor substrate between the channel regions.
摘要翻译：非易失性半导体存储器包括：单元阵列，其中在半导体衬底中使用具有源极和漏极区域的单元晶体管和半导体衬底上具有三层结构的栅电极的电可擦除可编程非易失性半导体存储器单元布置在矩阵形式。在具有三层结构的栅电极中，第一层浮置栅电极通过第一栅极绝缘膜与半导体衬底表面相对，并且第二或第三层栅极用作擦除和控制栅电极之一。擦除栅电极通过隧道绝缘膜与浮栅的一部分相对，并且控制栅电极通过第二栅极绝缘膜与浮栅电极相对。擦除和控制栅电极被布置成彼此平行并且垂直于源区和漏区。在沟道区域的长度方向上彼此相邻的两个单元晶体管中，一个单元晶体管的源极区域与另一个单元晶体管的漏极区域相同，并且在晶体管的宽度方向上彼此相邻的单元晶体管沟道区域通过形成在沟道区域之间的半导体衬底中的元件隔离区元件隔离。

74. 发明授权

US5034926A Non-volatile semiconductor memory 失效
标题翻译：非易失性半导体存储器
公开(公告)号：US5034926A
公开(公告)日：1991-07-23
申请号：US392070
申请日：1989-08-10
申请人： Tadayuki Taura , Masamichi Asano , Sadayuki Yokoyama
发明人： Tadayuki Taura , Masamichi Asano , Sadayuki Yokoyama
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/16
CPC分类号： G11C16/16 , G11C16/10
摘要： In a non-volatile semiconductor memory of this invention, a memory cell array constituted by a plurality of memory cells is divided into a plurlaity of blocks, and erase lines which are common to the respective blocks and independent from each other are arranged. In the data write mode, a predetermined voltage is applied to only the erase line connected to a selected one of the blocks.
摘要翻译：在本发明的非易失性半导体存储器中，由多个存储单元构成的存储单元阵列被划分为多个块，并且布置了各个块相互独立的擦除线。在数据写入模式中，只将预定电压施加到连接到所选择的一个块的擦除线。

75. 发明授权

US07139201B2 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US07139201B2
公开(公告)日：2006-11-21
申请号：US11243985
申请日：2005-10-06
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C11/34
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

76. 发明授权

US06781895B1 Non-volatile semiconductor memory device and memory system using the same 失效
标题翻译：非易失性半导体存储器件和使用其的存储器系统
公开(公告)号：US06781895B1
公开(公告)日：2004-08-24
申请号：US09722474
申请日：2000-11-28
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C700
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

77. 发明授权

US06172911B2 Non-volatile semiconductor memory device with an improved verify voltage generator 失效
标题翻译：具有改进的验证电压发生器的非易失性半导体存储器件
公开(公告)号：US06172911B2
公开(公告)日：2001-01-09
申请号：US09283583
申请日：1999-04-01
申请人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
发明人： Tomoharu Tanaka , Masaki Momodomi , Hideo Kato , Hiroto Nakai , Yoshiyuki Tanaka , Riichiro Shirota , Seiichi Aritome , Yasuo Itoh , Yoshihisa Iwata , Hiroshi Nakamura , Hideko Odaira , Yutaka Okamoto , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C1606
CPC分类号： G11C29/785 , G06F11/1008 , G06F11/1068 , G06F2201/81 , G06F2212/2022 , G11C16/10 , G11C16/12 , G11C16/24 , G11C16/3436 , G11C16/344 , G11C16/3454 , G11C29/34 , G11C29/52
摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite operation, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.
摘要翻译：可以缩短程序验证和擦除验证操作所需的时间。即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。在数据重写操作中，通过改变数据寄存器中的数据，对具有一次适当写入的数据的存储单元不进行重写操作。

78. 发明授权

US5761119A Nonvolatile semiconductor memory with a plurality of erase decoders connected to erase gates 失效
标题翻译：具有连接到擦除门的多个擦除解码器的非易失性半导体存储器
公开(公告)号：US5761119A
公开(公告)日：1998-06-02
申请号：US273922
申请日：1994-07-12
申请人： Masamichi Asano
发明人： Masamichi Asano
IPC分类号： G11C17/00 , G11C16/02 , G11C16/10 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/06
CPC分类号： H01L27/115 , G11C16/10 , G11C16/16 , H01L29/42328
摘要： A non-volatile semiconductor memory cell including: a plurality of blocks each having a plurality of floating gate transistors as memory cells, the floating gate transistor having a drain, a source, a floating gate, and a control gate capacitively coupled to the floating gate, and a data program of the floating gate transistor being effected by data write through injection of electrons into the floating gate and by data erase through emission of electrons from the floating gates; a circuit unit for applying an erase signal to a selected one of the blocks to emit electrons from the floating gates of a plurality of memory cells in the selected block and to erase data in all of the memory cells in the selected block at the same time; and a circuit unit for applying a write signal to the drains of the floating gate transistors within the selected block, without applying the write signal to the drains of the floating gate transistors of non-selected blocks.
摘要翻译：一种非易失性半导体存储单元，包括：多个块，每个块具有作为存储单元的多个浮置栅极晶体管，所述浮置栅极晶体管具有漏极，源极，浮置栅极和与所述浮动栅极电容耦合的控制栅极并且浮栅晶体管的数据程序通过通过将电子注入到浮置栅中的数据写入和通过从浮置栅极发射电子的数据擦除来实现; 电路单元，用于将擦除信号施加到所选块中的一个块，以从所选块中的多个存储单元的浮动栅极发射电子，并同时擦除所选块中的所有存储单元中的数据 ; 以及电路单元，用于将写信号施加到所选块内的浮栅晶体管的漏极，而不将写信号施加到未选块的浮栅晶体管的漏极。

79. 发明授权

US5436913A Non-volatile semiconductor memory device using successively longer write pulses 失效
标题翻译：使用连续更长写入脉冲的非易失性半导体存储器件
公开(公告)号：US5436913A
公开(公告)日：1995-07-25
申请号：US069911
申请日：1993-06-01
申请人： Toshio Yamamura , Hiroto Nakai , Hideo Kato , Kaoru Tokushige , Masamichi Asano
发明人： Toshio Yamamura , Hiroto Nakai , Hideo Kato , Kaoru Tokushige , Masamichi Asano
IPC分类号： G11C16/34 , G06F11/00
CPC分类号： G11C16/3459 , G11C16/3454
摘要： A non-volatile semiconductor memory device has writing part (203, 205, 209) for writing data in a non-volatile memory cell in response to a write pulse, readout part (419) for reading out data stored in the memory cell, and verification part (207, 210; 417) for verifying to ensure that normal writing has been completed by reading data from the memory cell after each writing. The device repeats writings unless a normal writing can be confirmed by the verification part. At this time, the writing part can vary writing time and in a part of a sequence of repeating writing unless a normal writing can be confirmed, it sets writing time longer for the next writing action than that for one writing action. Since this setting is performed according to constant multiplication, constant increment, or constant multiplication of accumulated value, necessary time for obtaining normal data write can be reduced.
摘要翻译：非挥发性半导体存储器件具有写入部分（203,205,209），用于响应写入脉冲在非易失性存储单元中写入数据，用于读出存储在存储器单元中的数据的读出部分（419）以及验证部件（207,210; 417），用于通过在每次写入之后从存储器单元读取数据来验证以确保正常写入已经完成。设备重复写入，除非验证部分可以确认正常写入。此时，写入部分可以改变写入时间，并且在重复写入序列的一部分中，除非正常写入可以被确认，否则为下一个写入动作设置比一个写入动作的写入时间更长的时间。由于根据常数乘法，常数增量或累积值的常数乘法执行该设置，因此可以减少获得正常数据写入所需的时间。

80. 发明授权

US5428569A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5428569A
公开(公告)日：1995-06-27
申请号：US38985
申请日：1993-03-29
申请人： Hideo Kato , Hiroto Nakai , Masamichi Asano , Kaoru Tokushige
发明人： Hideo Kato , Hiroto Nakai , Masamichi Asano , Kaoru Tokushige
IPC分类号： G11C17/00 , G11C16/02 , G11C16/12 , G11C16/16 , G11C29/00 , G11C29/12 , G11C29/24 , G11C29/50 , G11C29/52 , G11C7/00
CPC分类号： G11C16/12 , G11C16/16 , G11C29/50 , G11C29/52 , G11C16/04
摘要： A non-volatile semiconductor memory device comprises: a plurality of memory cells for electrically rewriting data; a programming and erasing section for executing data writing programs and data erasing operation for the memory cells; a verifying section for discriminating whether a data is written in or erased from one of the memory cells properly whenever data are written to or erased from the memory cells; and an automatic control section for enabling the programming and erasing section to execute the data writing program and erasing operation again whenever the verifying section discriminates that data is not properly written to or erased from one of the memory cells, the data writing program or erasing operation being executed repeatedly by the number of times less than a user-defined maximum program execution or erasing operation number applied externally from the outside of the memory device. Further, the number of data writing and erasing operations can be outputted to the outside of the chip. Therefore, it is possible to optimize the limit of the data writing operation according to the chip samples and to detect the deterioration status of he chip externally from the chip. The reliability of a system using the memory devices can be improved, and further the chip exchange timing can be indicated to the user.
摘要翻译：非挥发性半导体存储器件包括：用于电重写数据的多个存储单元; 用于对存储单元执行数据写入程序和数据擦除操作的编程和擦除部分; 一个验证部分，用于鉴别每当数据被从存储器单元写入或擦除时，正确地从一个存储器单元写入数据或从其中擦除数据; 以及自动控制部分，用于使编程和擦除部分能够每当验证部分识别数据未被正确地从存储器单元之一写入或擦除时执行数据写入程序和擦除操作，数据写入程序或擦除操作重复执行小于从存储装置的外部外部施加的用户定义的最大程序执行或擦除操作数的次数。此外，可以将数据写入和擦除操作的数量输出到芯片的外部。因此，可以根据芯片样本优化数据写入操作的限制，并且从芯片外部检测芯片的劣化状态。可以提高使用存储器件的系统的可靠性，并且可以向用户指示芯片交换定时。

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