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1. 发明授权

US5625591A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5625591A
公开(公告)日：1997-04-29
申请号：US445960
申请日：1995-05-22
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C29/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

2. 发明授权

US5579279A Semiconductor memory device and method of manufacturing the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5579279A
公开(公告)日：1996-11-26
申请号：US534108
申请日：1995-09-26
申请人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
发明人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
IPC分类号： G06F12/14 , G06F21/24 , G11C8/20 , G11C16/22 , G11C17/00 , G11C8/00 , G11C7/00 , G11C11/34
CPC分类号： G06F12/1408 , G11C16/22 , G11C8/20
摘要： A memory system having an input buffer, an address counter, an address decoder, and a memory-cell array. Address signals are supplied to the memory-cell array. In the system, a true-address data determining section has wires or a circuit storing an internal address specific to the system. A false-data generating circuit generates false data when the internal address is in a false data area, and the false data is input to an output selecting circuit. A true-address data area detecting circuit compares the true-address data EAi with the internal address consisting of the address signals supplied from an address counter, and generates a signal REAL when the internal address is in a true-address data area. The output-selecting circuit selects the false data or the data read from the memory-cell array through a sense amplifier, in accordance with whether the signal REAL is at high level or low level. The data stored in the memory-cell array consists of true data items and false data items. Hence, even if the data is copied into a conventional semiconductor memory device, it cannot be used in practice.
摘要翻译：具有输入缓冲器，地址计数器，地址解码器和存储单元阵列的存储器系统。地址信号被提供给存储单元阵列。在系统中，真实地址数据确定部分具有存储专用于系统的内部地址的电线或电路。假数据产生电路在内部地址处于假数据区域时产生假数据，并将错误数据输入到输出选择电路。真实地址数据区域检测电路将真实地址数据EAi与由地址计数器提供的地址信号组成的内部地址进行比较，并且当内部地址在真实地址数据区域中时产生信号REAL。输出选择电路根据信号REAL是高电平还是低电平，通过读出放大器选择伪数据或从存储单元阵列读出的数据。存储在存储单元阵列中的数据由真实数据项和假数据项组成。因此，即使将数据复制到常规的半导体存储器件中，也不能在实践中使用。

3. 发明授权

US5732022A Non-volatile semiconductor memory device 失效
公开(公告)号：US5732022A
公开(公告)日：1998-03-24
申请号：US812765
申请日：1997-03-06
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C16/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

4. 发明授权

US5576994A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5576994A
公开(公告)日：1996-11-19
申请号：US428060
申请日：1995-04-25
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C7/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

5. 发明授权

US5548559A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US5548559A
公开(公告)日：1996-08-20
申请号：US448852
申请日：1995-05-24
申请人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
发明人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
IPC分类号： G06F12/06 , G11C8/12 , G11C16/20 , G11C17/00 , G11C8/00
CPC分类号： G11C16/20 , G11C8/12
摘要： A semiconductor integrated circuit includes a chip address data designation circuit, which has nonvolatile circuit characteristics or nonvolatilely programmed wiring corresponding to a chip address assigned to each of semiconductor chips connected to common buses, to output first chip address data corresponding to the chip address upon receiving an operation power supply voltage. The semiconductor integrated circuit further includes a chip address data latch circuit for latching second chip address data supplied from outside to the semiconductor chip, and a chip selection control circuit for comparing the first chip address data and the second chip address data, and generating a chip selection signal for activating the semiconductor chip when the first chip address data and the second chip address data coincide with each other. The chip address assigned to each semiconductor chip can be stored nonvolatilely, and one of the chips can be selected in response to the chip address supplied from outside the chip.
摘要翻译：半导体集成电路包括芯片地址数据指定电路，其具有对应于分配给连接到公共总线的每个半导体芯片的芯片地址的非易失性电路特性或非易失性编程布线，以在接收时输出与芯片地址对应的第一芯片地址数据操作电源电压。半导体集成电路还包括用于锁存从外部向半导体芯片提供的第二芯片地址数据的芯片地址数据锁存电路，以及用于比较第一芯片地址数据和第二芯片地址数据的芯片选择控制电路，以及产生芯片当第一芯片地址数据和第二芯片地址数据彼此一致时激活半导体芯片的选择信号。分配给每个半导体芯片的芯片地址可以被非易失性地存储，并且可以响应于从芯片外部提供的芯片地址来选择一个芯片。

6. 发明授权

US5457650A Apparatus and method for reading multi-level data stored in a semiconductor memory 失效
标题翻译：用于读取存储在半导体存储器中的多电平数据的装置和方法
公开(公告)号：US5457650A
公开(公告)日：1995-10-10
申请号：US272682
申请日：1994-07-08
申请人： Nobutake Sugiura , Hideo Kato , Yoshio Mochizuki
发明人： Nobutake Sugiura , Hideo Kato , Yoshio Mochizuki
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8246 , H01L27/112 , G11C11/34
CPC分类号： G11C11/5692 , G11C11/56 , G11C11/5621 , G11C11/5642 , G11C16/08 , G11C16/32 , G11C2211/5642 , G11C8/14
摘要： A semiconductor memory includes memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.
摘要翻译：半导体存储器包括存储单元，字线，位线，行解码器，列解码器，电压改变电路，读出放大器和输出电路。每个存储单元存储多级数据。行解码器根据地址信号选择一个字线。电压变化电路产生施加到行解码器的不同电压。从电压变化电路依次施加不同的电压到由行解码器选择的字线。每当字线的电位变化时，列解码器选择位线。每次字线的电位改变时，读出放大器检测从存储单元读取到位线上的数据。输出电路将数据转换为代码数据。

7. 发明授权

US5852575A Apparatus and method for reading multi-level data stored in a semiconductor memory 失效
标题翻译：用于读取存储在半导体存储器中的多电平数据的装置和方法
公开(公告)号：US5852575A
公开(公告)日：1998-12-22
申请号：US819052
申请日：1997-03-18
申请人： Nobutake Sugiura , Hideo Kato , Yoshio Mochizuki
发明人： Nobutake Sugiura , Hideo Kato , Yoshio Mochizuki
IPC分类号： G11C11/56 , G11C16/02 , G11C16/04 , G11C16/06 , H01L21/8246 , H01L27/112 , G11C11/34
CPC分类号： G11C11/5692 , G11C11/56 , G11C11/5621 , G11C11/5642 , G11C16/08 , G11C16/32 , G11C2211/5642 , G11C8/14
摘要： A semiconductor memory including memory cells, word lines, bit lines, a row decoder, column decoder, a voltage-changing circuit, a sense amplifier, and an output circuit. Each memory cell stores multi-level data. The row decoder selects one of the word lines in accordance with an address signal. The voltage-changing circuit generates different voltages, which are applied to the row decoder. The different voltages are sequentially applied from the voltage-changing circuit to the word line selected by the row decoder. The column decoder selects a bit line every time the potential of the word line changes. The sense amplifier detects the data read from the memory cell onto the bit line every time the potential of the word line changes. The output circuit converts the data to code data.
摘要翻译：包括存储器单元，字线，位线，行解码器，列解码器，电压改变电路，读出放大器和输出电路的半导体存储器。每个存储单元存储多级数据。行解码器根据地址信号选择一个字线。电压变化电路产生施加到行解码器的不同电压。从电压变化电路依次施加不同的电压到由行解码器选择的字线。每当字线的电位变化时，列解码器选择位线。每次字线的电位改变时，读出放大器检测从存储单元读取到位线上的数据。输出电路将数据转换为代码数据。

8. 发明授权

US5506813A Semiconductor apparatus and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5506813A
公开(公告)日：1996-04-09
申请号：US235371
申请日：1994-04-29
申请人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
发明人： Yoshio Mochizuki , Hideo Kato , Nobutake Sugiura
IPC分类号： G11C16/04 , G11C11/56 , G11C17/12 , H01L21/822 , H01L21/8246 , H01L27/04 , H01L27/112 , G11C7/00 , H01L27/10
CPC分类号： H01L27/1126 , G11C11/56 , G11C11/5692 , G11C17/12 , H01L27/112 , G11C16/0491 , G11C16/24 , G11C7/18
摘要： In a semiconductor memory apparatus having a cell array structure wherein occurrence of leak current is reduced and a margin at the time of sensing is increased, a plurality of memory transistors arranged in a matrix and having any one of four thresholds constitute banks in a column direction. The banks constitute memory cell arrays. A main bit line of Al is connected to three sub-bit lines via first selection transistors. A main ground line of Al is connected to two sub-ground lines via second selection transistors. Bank selection lines and word lines are formed to cross the main bit line and main ground line. Gates of the selection transistors are connected to the selection lines, and one selection line is connected to one selection transistor. Each of the sub-bit lines and sub-ground lines has a column of memory transistors which constitute a bank. A separation region (not shown) of a silicon oxide film, etc. is formed between the memory cell arrays to prevent leak current. Thereby, an information amount per one element can be made equal to a plural-bit information amount, and the bit data capacity can be increased.
摘要翻译：在具有电池阵列结构的半导体存储装置中，其中泄漏电流的发生减少并且感测时的余量增加，以矩阵形式排列并具有四个阈值中的任一个的多个存储晶体管构成列方向。银行构成存储单元阵列。 Al的主位线通过第一选择晶体管连接到三个子位线。 Al的主地线通过第二选择晶体管连接到两个子接地线。银行选择行和字线形成为跨越主位线和主地线。选择晶体管的栅极连接到选择线，并且一个选择线连接到一个选择晶体管。每个子位线和子接地线具有构成一个存储体的一列存储晶体管。在存储单元阵列之间形成氧化硅膜的分离区（未示出）等，以防止漏电流。从而，可以使每一个元素的信息量等于多位信息量，并且可以增加位数据容量。

9. 发明授权

US5420822A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5420822A
公开(公告)日：1995-05-30
申请号：US218629
申请日：1994-03-28
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C7/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。

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