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1. 发明授权

US5420822A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5420822A
公开(公告)日：1995-05-30
申请号：US218629
申请日：1994-03-28
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C7/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。

2. 发明授权

US5732022A Non-volatile semiconductor memory device 失效
公开(公告)号：US5732022A
公开(公告)日：1998-03-24
申请号：US812765
申请日：1997-03-06
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C16/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.

3. 发明授权

US5576994A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5576994A
公开(公告)日：1996-11-19
申请号：US428060
申请日：1995-04-25
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C7/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

4. 发明授权

US5625591A Non-volatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US5625591A
公开(公告)日：1997-04-29
申请号：US445960
申请日：1995-05-22
申请人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
发明人： Hideo Kato , Nobutake Sugiura , Kiyotaka Uchigane , Masamichi Asano
IPC分类号： G11C8/08 , G11C16/16 , G11C16/28 , G11C16/34 , G11C29/50 , G11C29/00
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译：当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在打开内存单元。差分放大器用于检测列线的电位变化。在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平例如，各个单元的正方向。通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问，与常规装置相比。

5. 发明授权

US5381369A Nonvolatile semiconductor memory device using a command control system 失效
标题翻译：使用命令控制系统的非易失性半导体存储器件
公开(公告)号：US5381369A
公开(公告)日：1995-01-10
申请号：US191334
申请日：1994-02-03
申请人： Shinichi Kikuchi , Kiyotaka Uchigane , Hideo Kato
发明人： Shinichi Kikuchi , Kiyotaka Uchigane , Hideo Kato
IPC分类号： G11C16/22 , G11C7/00
CPC分类号： G11C16/22
摘要： A nonvolatile semiconductor memory device using a command control system comprises a protect cell composed of a nonvolatile memory cell, a protect sense amplifier circuit for reading the data from the protect cell, a high-voltage sensing circuit for supplying a voltage during a programmed operation such as a writing or an erasing operation, a protect control circuit for controlling the protect cell, and a control circuit for reading the data from the protect cell and according to the read-out data, controlling the command to the memory cell array.
摘要翻译：使用命令控制系统的非易失性半导体存储器件包括由非易失性存储单元组成的保护单元，用于从保护单元读取数据的保护读出放大器电路，用于在编程操作期间提供电压的高电压感测电路，作为写入或擦除操作，用于控制保护单元的保护控制电路，以及用于从保护单元读取数据并根据读出数据控制对存储单元阵列的命令的控制电路。

6. 发明授权

US07564717B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07564717B2
公开(公告)日：2009-07-21
申请号：US11923200
申请日：2007-10-24
申请人： Kazuhiko Sato , Hidetoshi Saito , Kiyotaka Uchigane
发明人： Kazuhiko Sato , Hidetoshi Saito , Kiyotaka Uchigane
IPC分类号： G11C11/34
CPC分类号： G11C16/30 , H02M3/073 , H02M2003/077
摘要： A semiconductor memory device includes a memory cell array, word lines each of which connects the control gates of the memory cells on the same row together in the memory cell array, a row decoder which selects a word line, and applies a voltage to the selected word line, and a voltage generator which generates a boosted voltage, and outputs the boosted voltage as the voltage, the voltage generator includes a comparator which compares a first voltage with a second voltage, and outputs a comparison result signal, a constant current circuit which generates a first control signal in accordance with the comparison result signal, a first delay circuit which generates a second control signal by delaying the comparison result signal, and a charge pump circuit which generates the boosted voltage in response to the first and second control signals.
摘要翻译：一种半导体存储器件，包括一个存储单元阵列，每个都将存储单元阵列中同一行上的存储单元的控制栅极连接在一起的字线，选择字线的行译码器，字线和产生升压电压的电压发生器，并输出升压电压作为电压，电压发生器包括将第一电压与第二电压进行比较的比较器，并输出比较结果信号;恒流电路，根据比较结果信号产生第一控制信号，通过延迟比较结果信号产生第二控制信号的第一延迟电路和响应于第一和第二控制信号产生升压电压的电荷泵电路。

7. 发明申请

US20050184771A1 Semiconductor apparatus 审中-公开
标题翻译：半导体装置
公开(公告)号：US20050184771A1
公开(公告)日：2005-08-25
申请号：US11017750
申请日：2004-12-22
申请人： Kiyotaka Uchigane , Tomohito Kawano
发明人： Kiyotaka Uchigane , Tomohito Kawano
IPC分类号： G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04 , H03K17/22 , H03L7/00
CPC分类号： H03K17/223
摘要： A semiconductor device is disclosed, which comprises a voltage dividing resistor circuit including a plurality of resistor elements connected in series between a power supply node and a ground node, a voltage detecting PMOS transistor having a gate connected to an output node of the voltage dividing resistor circuit and a source connected to the power supply node, a resistor element connected between a drain of the voltage detecting PMOS transistor and a ground node, a CMOS inverter circuit supplied with a power supply voltage through the power supply node, having an input terminal connected to a drain of the voltage detecting PMOS transistor and an output terminal for outputting a power-on detection signal, and a monitoring pad which monitors a potential of the output node of the voltage dividing resistor circuit from exterior of a semiconductor chip.
摘要翻译：公开了一种半导体器件，其包括分压电阻器电路，其包括串联连接在电源节点和接地节点之间的多个电阻元件，电压检测PMOS晶体管，其栅极连接到分压电阻器的输出节点电路和连接到电源节点的源极，连接在电压检测PMOS晶体管的漏极和接地节点之间的电阻元件，经由电源节点提供有电源电压的CMOS反相器电路，具有连接的输入端子到电压检测PMOS晶体管的漏极和用于输出上电检测信号的输出端子，以及监控焊盘，其从半导体芯片的外部监视分压电阻器电路的输出节点的电位。

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