专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

71. 发明专利

JPS5726487A Semiconductor laser device 失效
标题翻译：半导体激光器件
公开(公告)号：JPS5726487A
公开(公告)日：1982-02-12
申请号：JP9991880
申请日：1980-07-23
申请人： Hitachi Ltd
发明人： YAMASHITA SHIGEO , MATSUDA HIROSHI , KOBAYASHI UICHIROU , KOBAYASHI MASAYOSHI , NAKASHIMA HISAO
IPC分类号： H01S5/00 , H01S5/227
CPC分类号： H01S5/227 , H01S5/2275
摘要： PURPOSE: To stably oscillate a semiconductor laser device in a basic mode by decreasing the width of an active layer smaller than that of a light guide layer capable of existing laser light.
CONSTITUTION: An N type clad layer 1, an N type light guide layer 2, an active layer 3, a P type clad layer 4 and a buried layer 6 are formed on a semiconductor substrate 10. In the semiconductor laminated layer, the position of the layer 3 is located under the neck position 14 of the mesa semiconductor layer. Thus, the width of the layer 3 can be reduced than that of the layer 2 capable of existing laser light, and stable oscillation can be obtained readily in the basic mode. When the refractive indexes of the layers 1∼4 are n
1 ∼n
4 , it is constructed to have n
3 >n
2 >n
1 , n
4 . The laser light can be distributed in the layers 3, 2 with this relation of the refractive indexes, the light output can be increased. On the other hand, the relation of the forbidden band widths Eg
1 ∼Eg
3 of the layers 1∼3 is Eg
3 1 , Eg
2 , the carrier enclosure in the layer 3 can be sufficiently performed.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：通过减少有源层的宽度比能够存在激光的导光层的宽度，以基本模式稳定地振荡半导体激光器件。构成：在半导体衬底10上形成N型覆盖层1，N型导光层2，有源层3，P型覆盖层4和掩埋层6.在半导体层叠层中，层3位于台面半导体层的颈部位置14的下方。因此，可以比能够存在激光的层2的宽度减小，在基本模式下可以容易地获得稳定的振荡。当层1-4的折射率为n1-n4时，其构造为具有n3> n2> n1，n4。激光可以以这种折射率的关系分布在层2,3中，可以增加光输出。另一方面，层1-3的禁带宽度Eg1-Eg3的关系为Eg3

72. 发明专利

JPS51124403A OPTICAL RECORDING SYSTEM 失效
公开(公告)号：JPS51124403A
公开(公告)日：1976-10-29
申请号：JP4867275
申请日：1975-04-23
申请人： HITACHI LTD
发明人： MEGUMI KOUICHI , KOZUKA KOUJI , KOBAYASHI MASAYOSHI , FURUHATA YOSHIO
IPC分类号： G02F1/03 , G02F1/05 , G11B7/243 , G11C11/42
摘要： PURPOSE:To record informations with high efficiency, and their taking out and erasing by use of Injury Electro-optical Crystal as an information recording device in Optical Recording System.

73. 发明专利

JP2009071009A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2009071009A
公开(公告)日：2009-04-02
申请号：JP2007237447
申请日：2007-09-13
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MATSUURA KATSUYA , ODA TETSUO , KOBAYASHI MASAYOSHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/739
摘要： PROBLEM TO BE SOLVED: To provide a structure capable of leading out trench-side wall gate withstand voltage normally for a semiconductor device in which a gate lead-out electrode is connected to an in-trench buried gate electrode.
SOLUTION: The semiconductor device 20 having a gate insulating film 8 covering an internal surface of a trench 7 formed on a semiconductor substrate 15 and the gate electrode 10 buried in the trench 7 has field insulating films 9 disposed on both sides across a portion of the trench 7 along the width and having forward tapered field slopes 9c and having thickness thicker than that of the gate insulating film 8, and a gate lead-out electrode 10a connected to the gate electrode 10 and disposed on the field slopes 9c on both the sides of the trench 7, wherein the trench 7 has forward tapered trench slopes 7a on side surfaces and is provided with a gate insulating film 8 above the trench slopes 7a, and the gate insulating film 8 and field insulating films 9 come into contact with each other above a portion of the trench 7.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种能够将栅极引出电极连接到沟槽内的栅极电极的半导体器件正常引出沟槽侧壁栅极耐受电压的结构。解决方案：具有覆盖半导体衬底15上形成的沟槽7的内表面的栅极绝缘膜8和掩埋在沟槽7中的栅电极10的半导体器件20具有设置在两侧的场绝缘膜9 沿着宽度的沟槽7的一部分，并且具有比栅极绝缘膜8厚的厚度的正锥形磁场斜率9c，以及连接到栅电极10并设置在场斜面9c上的栅极引出电极10a 沟槽7的两侧，其中沟槽7在侧表面上具有向前的锥形沟槽斜面7a，并且在沟槽斜面7a上方设置有栅极绝缘膜8，并且栅极绝缘膜8和场绝缘膜9接触彼此在沟槽7的一部分之上。版权所有（C）2009，JPO＆INPIT

74. 发明专利

JP2008177279A Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2008177279A
公开(公告)日：2008-07-31
申请号：JP2007008107
申请日：2007-01-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ODA TETSUO , KOBAYASHI MASAYOSHI , MATSUURA KATSUYA , TAKAYANAGI YUJI , KAWASE DAISUKE
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a method for stably manufacturing semiconductor device such as a trench gate type MOS transistor that is not easily affected by a defect resulting from variation in manufacturing processes and assures small variation in the threshold voltages among semiconductor devices.
SOLUTION: In the method for manufacturing semiconductor device including a first conductive semiconductor layer, a second conductive channel region on the front surface of the same semiconductor layer, a first conductive source region on the front surface of the channel region, a trench region extended to the semiconductor layer from the source region through the channel region, a gate insulating film of the trench region, and a gate electrode, the channel region is formed by conducting the predetermined heat treatment after ion injection of an impurity, an acceleration voltage in the ion injection is in the range of 200 to 300 keV, and the predetermined heat treatment is continued for 30 to 600 minutes under the temperature range of 1,000 to 1,200°C in the non-oxidizing atmosphere.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于稳定地制造诸如沟槽栅型MOS晶体管的半导体器件的方法，其不容易受到由制造工艺的变化引起的缺陷的影响，并且确保半导体器件中的阈值电压的小的变化。解决方案：在包括第一导电半导体层的半导体器件的制造方法中，在同一半导体层的前表面上的第二导电沟道区，沟道区的前表面上的第一导电源区，沟槽通过沟道区域从源极区域延伸到半导体层，沟槽区域的栅极绝缘膜和栅电极，通过在离子注入杂质之后进行预定热处理形成沟道区域，加速电压离子注入的范围为200〜300keV，在非氧化性气氛中，在1000〜1200℃的温度范围内，进行规定的热处理持续30〜600分钟。版权所有（C）2008，JPO＆INPIT

75. 发明专利

JP2003258003A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003258003A
公开(公告)日：2003-09-12
申请号：JP2002059905
申请日：2002-03-06
申请人： HITACHI LTD
发明人： TAKAZAWA HIROYUKI , TAKATANI SHINICHIRO , YAMANE MASAO , KOBAYASHI MASAYOSHI
IPC分类号： H01L29/812 , H01L21/335 , H01L21/338 , H01L29/06 , H01L29/778 , H01L31/0328 , H01L31/0336 , H01L31/072
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for use at high frequencies which exhibits a high dielectric breakdown voltage, and to provide its manufacturing method. SOLUTION: A region 11 including a heavily-doped semiconductor of a first conductivity-type and a region 12 including a lightly-doped semiconductor of a first conductivity-type are provided on the side of a barrier layer 5 farther away from a semiconductor substrate 1 than its end opposite to the semiconductor substrate 1 and between an ohmic layer 7 and a gate electrode 10. The sheet impurity concentration of the region 12 is set lower than the sheet impurity concentration between the bottom face of the gate electrode 10 on the side of the semiconductor substrate 1 and the end face of a channel layer 3 opposite to the semiconductor substrate 1. Additionally, the sheet impurity concentration of the region 11 is set higher than the sheet impurity concentration of the region 12. Consequently, a semiconductor device exhibiting a high dielectric voltage for use at high frequencies can be obtained. COPYRIGHT: (C)2003,JPO

76. 发明专利

JP2003124233A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003124233A
公开(公告)日：2003-04-25
申请号：JP2002226991
申请日：2002-08-05
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NUMAZAWA SUMUTO , NAKAZAWA YOSHITO , KOBAYASHI MASAYOSHI , KUDO SATOSHI , IMAI YASUO , KUBO SAKAE , SHIGEMATSU TAKU , ONISHI AKIHIRO , UESAWA KOUZOU , OISHI KENTARO
IPC分类号： H01L21/316 , H01L21/336 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To solve the problem that reliability in a semiconductor device having a MISFET of a trench gate structure is lowered. SOLUTION: In a method for manufacturing a semiconductor device having a MISFET of a trench gate structure, a groove 4 is formed of a main plane of a first conductive type semiconductor layer 1B as a drain area to the depth direction thereof, and a gate insulating film 5 composed of a thermal oxide film 5A and a deposited film 5B on the internal plane of the groove 4 is formed, and a gate electrode 6A is formed in the groove 4. Thereafter, impurities are introduced into the first conductive type semiconductor layer 1B to form a second conductive type semiconductor area 8 as a channel forming area, and impurities are introduced into the second conductive type semiconductor area 8 to form a first conductive type semiconductor area 9 as a source area.

77. 发明专利

JP2001217211A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND DICING DEVICE 失效
公开(公告)号：JP2001217211A
公开(公告)日：2001-08-10
申请号：JP2000027471
申请日：2000-02-04
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： NAKANISHI MASAKI , KOBAYASHI MASAYOSHI
IPC分类号： B28D5/02 , H01L21/301
摘要： PROBLEM TO BE SOLVED: To dice a semiconductor wafer provided with a back surface electrode. SOLUTION: A dicing device 20 is provided with a fine first diamond blade 28 and a coarse second diamond blade 29, both of which are arranged in the same vertical plane. At the time of dicing a wafer 14 provided with a back electrode 10, a first cut groove 31 is formed by cutting a brittle substrate 2 with the first blade 28 while preventing occurrence of chippings. Then, a second cut groove 32 is formed from the first cut groove by cutting the ductile electrode 10 with the second blade 29 while the occurrence of clogging is prevented. Since the whole body of the wafer 14 including the back electrode 10 can be cut appropriately with the diamond blades 28 and 29 while the occurrence of clogging is prevented, the manufacturing cost of a semiconductor device can be reduced. In addition, when the electrode 10 is formed by performing electroplating on the entire rear surface of the substrate 2 without using selective plating, the manufacturing cost of the device can be reduced more.

78. 发明专利

JPH1174514A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH1174514A
公开(公告)日：1999-03-16
申请号：JP23242597
申请日：1997-08-28
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： NUMAZAWA SUMUTO , NAKAZAWA YOSHITO , KOBAYASHI MASAYOSHI , KUDO SATOSHI , IMAI YASUO , KUBO SAKAE , SHIGEMATSU TAKU , OONISHI SHIYOUKOU , UESAWA KOUZOU , OISHI KENTARO
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device having a MISFET of trench gate structure. SOLUTION: A method for manufacturing a semiconductor having a MISFET of trench gate structure is composed of a process for forming holes 4 from the major surface of a first conductive semiconductor layer 1B which is a drain area in the direction of its depth, a process for forming a gate insulating film 5 composed of a thermal-oxidized film 5A and a deposited film 5B on the inner surface of each of the holes 4, a process for forming a gate electrode 6A in each of the holes 4 and a process for forming a second conductive semiconductor area 8 as an area for forming channel by introducing impurities in the first conductive semiconductor layer 1B and forming a first conductive semiconductor area 9 as a source area by introducing impurities in the second conductive semiconductor area 8.

79. 发明专利

JPH10270689A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10270689A
公开(公告)日：1998-10-09
申请号：JP7706897
申请日：1997-03-28
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI CHIYOU LSI SYS KK
发明人： YANOKURA EIJI , SUZUKI HIROISA , OTAKA SHIGEO , IIJIMA TETSUO , KUDO SATOSHI , MACHIDA NOBUO , KOBAYASHI MASAYOSHI , NUMAZAWA SUMUTO , SAKAMOTO MITSUZO , KANAZAWA TAKAMITSU
IPC分类号： H01L29/06 , H01L29/12 , H01L29/423 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To improve the gate breakdown voltage and on-resistance, and the high-speed switching characteristic by dividing a major surface of a semiconductor substrate into octagons by the groove of a trench gate, and making each interior angle of these octagons a specific angle. SOLUTION: In a semiconductor device, a major surface of a semiconductor substrate is divided into flat octagons by the groove of a trench gate 4. And each interior angle of these octagons is approximately 135 degrees, and the side surface of the principal surface of the semiconductor substrate divided into the flat octagons is 1, 0, 0} or 1, 1, 0} surface. By dividing the major surface of the semiconductor substrate into flat octagonal planes in this way, the angles of corners formed on the side surfaces of the major surface of the semiconductor substrate divided become obtuse, and the shapes of silicon oxide films to be gate insulating films become more uniform. Consequently, it becomes possible to prevent the breakdown voltages from lowering by the defects of these parts of the insulating films.

80. 发明专利

JPH03270243A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03270243A
公开(公告)日：1991-12-02
申请号：JP7159590
申请日：1990-03-20
申请人： HITACHI LTD
发明人： KOBAYASHI MASAYOSHI
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/338 , H01L29/812
摘要： PURPOSE:To reduce environmental contamination due to semiconductor processes by using CF4, NF3, or mixed gas SF6 and Cl2 when the area between source and drain electrodes on a GaAs cap layer is selectively etched to expose an active layer for forming a gate electrode. CONSTITUTION:GaAs cap layers 3 are formed on an active layer 2, and a source electrode 4 and a drain electrode 5 are formed and isolated. The area between the source and drain is selectively etched with CF4, NF3, or mixed gas SF6 and Cl2 to expose the active layer 2, and a gate electrode is formed. Since such a gas consisting of CF4, NF3 and SF6 mixed gas, instead of CCl2F2, is used in the selective etching, it is possible to reduce environmental contamination and effects on the ozone layer while improving the performance of a high- electron-mobility transistor.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式