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71. 发明专利

JPH0381235B2 失效
公开(公告)号：JPH0381235B2
公开(公告)日：1991-12-27
申请号：JP26378587
申请日：1987-10-21
申请人： HITACHI LTD
发明人： ITO KYOO , HORI RYOICHI
IPC分类号： G11C11/409 , G11C11/34 , G11C11/401 , G11C11/41

72. 发明专利

JPH0316081A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0316081A
公开(公告)日：1991-01-24
申请号：JP12671290
申请日：1990-05-18
申请人： HITACHI LTD
发明人： ITO KIYOO , HORI RYOICHI
IPC分类号： G11C11/401
摘要： PURPOSE:To attain a high speed and to increase the degree of freedom for a design of the device by using a memory array division and a common signal line. CONSTITUTION:One piece of data line is divided into D00 - D03, and on a part of each divided data line, switches SW00 - SW03 controlled by an output control signal YC0 by a Y decoder and a Y driver (YDEC) are provided, and data is given and received between the divided data lines belonging to the other and common input/output lines I/O(0) - I/O(3). In this case, since the data line is fractionalized, a read-out signal of a high output voltage is obtained at a high speed to the data line D00 from a memory cell MC by by a word voltage appearing in a selective word line W by an X decoder and a word driver (XDEC). In such a way, a high speed and high integration memory can be realized.

73. 发明专利

JPH02263388A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH02263388A
公开(公告)日：1990-10-26
申请号：JP4101090
申请日：1990-02-23
申请人： HITACHI LTD
发明人： ITO KIYOO , HORI RYOICHI
IPC分类号： G11C11/409 , G11C11/401 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To facilitate the constitution of a large scale integrated circuit at a high speed by dividing a memory array into many arrays, providing a common signal line being common to plural data lines, and connecting the data line and the common signal line. CONSTITUTION:In a memory for forming a memory array, one piece of data line is divided as D00 - D03 shown in the figure, and on a part of each data line which is divided, switches SW00 - SW03 controlled by an output control signal YC0 by a Y decoder and a Y driver (YDEC) are provided, so that data can be given and received between a divided data line D10 belonging to the other and common input/output lines I/O (0) - I/O (3). In this case, since the data lines D00 - D03 are subdivided, a word voltage appears in a selection word line W by an X decoder and a word driver (XDEC). In such a way, a read-out signal of a high output voltage is obtained at a high speed from a memory cell MC to the data line D00.

74. 发明专利

JPH023152A DRIVING CIRCUIT 失效
公开(公告)号：JPH023152A
公开(公告)日：1990-01-08
申请号：JP14576488
申请日：1988-06-15
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KATO SHISEI , WATANABE TAKAO , HORI RYOICHI , KITSUKAWA GORO , KAWAJIRI YOSHIKI , KAWAHARA TAKAYUKI , ITO KIYOO
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To stably execute the switching action of a next stage circuit and to suppress a through current by controlling an output voltage by a capacity connected to an output terminal. CONSTITUTION:For a plate capacity 11, one electrode is connected to an output terminal 2 and the other is connected to a control signal phi synchronizing with an input terminal 1. Then, when an input signal V1 is changed from 'H' to 'L', an output voltage V0 rises rapidly. Next, when the signal phi is changed from 'L' to 'H', the voltage V0 rises by the capacity coupling of the V0 and the phi by the capacity 11. Thus, the 'H' level of the output voltage of a BiCMOS circuit is set to a requested voltage by capacities C11, C1 and a voltage Vphi.

75. 发明专利

JPH01261922A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01261922A
公开(公告)日：1989-10-18
申请号：JP8906188
申请日：1988-04-13
申请人： HITACHI LTD , HITACHI DEVICE ENG
发明人： KATO SHISEI , WATABE TAKAO , HORI RYOICHI , KITSUKAWA GORO , KAWAJIRI YOSHIKI , KAWAHARA TAKAYUKI , ITO KIYOO
IPC分类号： G11C11/417 , G11C11/34 , G11C11/414 , H03K5/02 , H03K19/00
摘要： PURPOSE:To enlarge a margin with respect to noise and to improve reliability by making the logical threshold voltage of at least one of CMOS circuits and of at least one of BiCMOS circuits almost similar. CONSTITUTION:For making the logical threshold voltage VTLB of the BiCMOS circuits half a power voltage, for example, the base voltage V15 of a bipolar transistor 8 comes to 1/2VCC+VBE when an input V1 and an output V0 shows 1/2VCC. Since (p) and (n) channel MOS transistors 4 and 5 generate a CMOS inverter and the output voltage shows V15, V15 can be set to 1/2VCC+VBE by appropriately deciding the ratio of respective gate widths. On the other hand, the logical threshold voltage VTLC can be set to 1/2VCC in the CMOS inverter by appropriately selecting the ratio of the gate widths of (p) and (n) channel MOS transistors 13 and 14. Thus, a noise margin becomes maximum and the reliability of a semiconductor device can be improved.

76. 发明专利

JPH01164064A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01164064A
公开(公告)日：1989-06-28
申请号：JP32137687
申请日：1987-12-21
申请人： HITACHI LTD
发明人： KOBAYASHI YUTAKA , TANBA AKIHIRO , HORI RYOICHI , ASAYAMA MASAICHIRO , NAMETAKE MASATAKE , MIYAZAWA HIROYUKI , YANAGISAWA KAZUMASA , KITSUKAWA GORO
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/94
摘要： PURPOSE:To reduce parasitic capacitance of a bipolar and to realize a high- speed operation by a method wherein the inside of a groove for isolation use is kept in a floating state from a surrounding semiconductor region by using an insulating film, an insulating layer and a conductive layer are formed alternately inside a groove for capacitance formation use of a memory cell and one conductive layer which is formed capacitance between faced conductive layers is connected to a fixed potential. CONSTITUTION:A P region 33 formed by ion implantation and an N region 62 formed by diffusion are formed at the bottom of a groove 32 for capacitance formation use of a memory cell; N polycrystalline Si 34 is separated from a P-substrate 10 by using a P-N junction so that its potential (anode potential) can be selected arbitrarily. In a device isolation groove 12, polycrystalline Si 15 is kept in a floating state by using insulating films 16; this prevents parasitic capacitance from being generated between collector regions 63 of a bipolar.

77. 发明专利

JPH01120053A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01120053A
公开(公告)日：1989-05-12
申请号：JP27581487
申请日：1987-11-02
申请人： HITACHI LTD
发明人： KAWAHARA TAKAYUKI , HORI RYOICHI , KITSUKAWA GORO , KAWAJIRI YOSHIKI , WATABE TAKAO , ITO KIYOO , HIGUCHI HISAYUKI
IPC分类号： H01L29/73 , G11C11/409 , H01L21/331 , H01L21/822 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L29/72 , H01L29/732 , H03K19/08
摘要： PURPOSE:To obtain a semiconductor device which can surely prevent a bipolar transistor from being saturated by installing a means to supply a base current of the bipolar transistor at a potential at which the bipolar transistor is not saturated. CONSTITUTION:In a semiconductor device containing at least one piece of a bipolar transistor Q, a means to supply a base current of at least one bipolar transistor of the bipolar transistor Q at a potential at which the bipolar transistor is not saturated is installed. For example, in a semiconductor device which contains a bipolar transistor Q11 used to charge an output terminal O from a high-voltage power supply VH and a bipolar transistor Q12 used to discharge the output terminal O to a low-voltage power supply VL, a circuit C1 used to supply a base current of the bipolar transistor Q11 at a potential in a range where the Q11 is not saturated and a circuit C2 used to supply a base current of the bipolar transistor Q12 at a potential in a range where the Q12 is not saturated are installed.

78. 发明专利

JPS6488992A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6488992A
公开(公告)日：1989-04-03
申请号：JP24373287
申请日：1987-09-30
申请人： HITACHI LTD
发明人： KAWAJIRI YOSHIKI , HORI RYOICHI , KITSUKAWA GORO , WATABE TAKAO , KAWAHARA TAKAYUKI , ITO KIYOO
IPC分类号： G11C11/407 , G11C11/34
摘要： PURPOSE:To obtain a timing pulse having a stable phase time by charging and discharging capacity with constant current and delaying a signal in a delay circuit generating the other signal after a fixed time when it receives an inputted signal. CONSTITUTION:A semiconductor integrated circuit is constituted by a constant voltage circuit, a constant current circuit, switches SW1 and SW2, the capacity C and a level detection circuit. When it is operated, the input IN is set at a low level, the inverse input IN is set at a high level, the SW1 is turned on, the SW2 is turned off and constant voltage generated by the constant voltage circuit is charged to the capacity C. At such a time, the level detection circuit is not operated and the output OUT is the low level. Then, when the input IN is changed to the high level and the inverse input IN is changed to the low level, the SW1 is turned OFF and the SW2 is turned on. Besides, electric charge accumulated in the capacity C is discharged in a fixed current (i) through the SW2 by the constant current circuit, the voltage of a node 10 falls in a straight line and the output OUT is raised to the high level by the level detection circuit when the voltage is fixed.

79. 发明专利

JPS62213153A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62213153A
公开(公告)日：1987-09-19
申请号：JP5476986
申请日：1986-03-14
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , TAKEDA EIJI , ITO KIYOO , HORI RYOICHI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To control currents between electrodes having a wide facing area, and to prevent the interference of signals between memory cells such as solid capacitor cells by specifying the shape of a groove or stipulating the relationship of substrate concentration, a distance between adjacent grooves, etc., in a memory cell using the side wall section of the groove in an Si substrate as an electrode surface for a capacitor. CONSTITUTION:When the conditions of L>W/2 are satisfied in an interval L with a capacitor oppositely faced to a capacitor 1 in (w) width and (d) depth to the capacitor 1, currents between these two capacitors can be controlled by substrate voltage VBB, and currents can be inhibited at an extremely small value by setting VBB within a proper range. Currents between the capacitors can also be reduced exceedingly by the impurity concentration NB of a layer wrapping a groove shaping the capacitor 1 and by setting the interval under predetermined conditions between the capacitor and the adjacent capacitor. Accordingly, informations between the adjacent capacitors do not interfare, thus normally operating a memory cell.

80. 发明专利

JPS62185363A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS62185363A
公开(公告)日：1987-08-13
申请号：JP2587386
申请日：1986-02-10
申请人： HITACHI LTD
发明人： TAKEDA EIJI , KIMURA KATSUTAKA , HORI RYOICHI , SHIMOHIGASHI KATSUHIRO , ITO KIYOO
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To reduce software errors of a semiconductor device by connecting the gate, source, drain of FETs connected with bit lines in a self-alignment, and forming its diffused layer in an HiC structure or a different conductivity type impurity under the diffused layer. CONSTITUTION:When a dynamic RAM is read out, the floating time of a bit line (data line) until a sense amplifier is positively operated after the bit line is precharged is important for software errors. A memory cell connected with a floating bit line, the source, drain layers of and wiring of an FET of a periphearl circuit are mostly covered with a P type layer 11 in a so-called HiC structure. The source, drain are connected with a gate in a self-alignment, and a diffused layer is contracted to approx. 1/3. In this case, polysilicon, high melting point metal or its silicide 19 is laid in a connecting hole and the periphery of the hole, aluminum wirings 20 are formed and connected with a diffused layer 12. When the layer 12 is N N structure 12-1, a P type layer is formed at the outside, and a density distribution is determined by N P type junction withstanding voltage and the ratio of software reduction.

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