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1. 发明授权

US3703710A Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US3703710A
公开(公告)日：1972-11-21
申请号：US3703710D
申请日：1971-01-04
申请人： HITACHI LTD
发明人： KUBO MASAHARU , HORI RYOICHI , NAGATA MINORU
IPC分类号： G11C5/14 , G11C11/412 , G11C11/417 , G11C11/40 , H03K3/286
CPC分类号： G11C5/14 , G11C11/412 , G11C11/417
摘要： A semiconductor memory comprising semiconductor elements organized into a plurality of sub-systems individually provided with respective power supply switches each actuated in synchronism with or in response to the select signal to the corresponding sub-system, whereby a predetermined amount of power is supplied only to the selected sub-system while the remaining sub-systems receive no power or just sufficient power to maintain their memory content.
摘要翻译：一种半导体存储器，包括组织成多个子系统的半导体元件，每个子系统分别设置有相应的电源开关，每个电源开关与选择信号同步或响应于相应的子系统而被致动，由此仅将预定量的电力仅供应到所选择的子系统，而其余的子系统不接收电力或仅接收足够的电力来维持其存储器内容。

2. 发明专利

SG59995A1 Semiconductor device 未知
公开(公告)号：SG59995A1
公开(公告)日：1999-02-22
申请号：SG1996009506
申请日：1986-11-12
申请人： HITACHI LTD
发明人： HORI RYOICHI , ITOH KIYOO , SHIMOHIGASHI KATSUHIRO
IPC分类号： H01L21/761 , H01L21/76 , H01L21/8238 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/08 , H01L29/78
摘要： The device has a buried layer under a memory array (1120) and arranged between a substrate and a semiconductor layer. A region is formed in the semiconductor layer between the array and a bipolar transistor. The region contacts the buried layer and extends up to main surface of the semiconductor layer. Another buried layer is provided under the bipolar transistor, and arranged between the semiconductor substrate and layer. The memory array on the main surface of a semiconductor layer has a number of memory cells each with a metal insulated semiconductor field effect transistor (MISFET) and a capacitor. The former buried layer is of same conductivity type as that of the semiconductor substrate and impurity concentration higher than that of the semiconductor substrate. Another buried layer has the same conductivity type as that of the semiconductor region.

3. 发明专利

DE3485234D1 未知
公开(公告)号：DE3485234D1
公开(公告)日：1991-12-12
申请号：DE3485234
申请日：1984-06-14
申请人： HITACHI LTD
发明人： HORI RYOICHI , ITOH KIYOO , ETOH JUN
IPC分类号： G11C11/419 , G11C11/401 , G11C11/409 , H03K19/017 , H03K19/0185 , H03K5/02
摘要： The present invention concerns a pulse drive circuit in which a primary voltage (Vcc) is supplied as a supply voltage, and which converts primary pulses (0i) of that primary voltage into secondary pulses (0il) of a secondary voltage which is different from the primary voltage; and a transistor (QL) which is supplied with the secondary pulses as controlling pulses, and with the primary voltage as a supply voltage, and which supplies to a load (CL) an electric potential limited by the secondary voltage.

4. 发明专利

DE2809233A1 未知
公开(公告)号：DE2809233A1
公开(公告)日：1978-09-07
申请号：DE2809233
申请日：1978-03-03
申请人： HITACHI LTD
发明人： HORI RYOICHI , KUBO MASAHARU , HASHINOTO NORIKAZU , NISHIMATSU SHIGERU , ITOH KIYOO
IPC分类号： H01L27/10 , H01L21/3213 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L27/115 , H01L29/78 , H01L21/90

5. 发明专利

HK1003586A1 Semiconductor device 未知
公开(公告)号：HK1003586A1
公开(公告)日：1998-10-30
申请号：HK98102615
申请日：1998-03-27
申请人： HITACHI LTD
发明人： KITSUKAWA GORO , ITOH KIYOO , HORI RYOICHI , WATANABE TAKAO , SHIMOHIGASHI KATSUHIRO , HOMMA NORIYUKI
IPC分类号： H01L21/761 , H01L21/76 , H01L21/8238 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L
摘要： The device has a buried layer under a memory array (1120) and arranged between a substrate and a semiconductor layer. A region is formed in the semiconductor layer between the array and a bipolar transistor. The region contacts the buried layer and extends up to main surface of the semiconductor layer. Another buried layer is provided under the bipolar transistor, and arranged between the semiconductor substrate and layer. The memory array on the main surface of a semiconductor layer has a number of memory cells each with a metal insulated semiconductor field effect transistor (MISFET) and a capacitor. The former buried layer is of same conductivity type as that of the semiconductor substrate and impurity concentration higher than that of the semiconductor substrate. Another buried layer has the same conductivity type as that of the semiconductor region.

6. 发明专利

DE3378662D1 SEMICONDUCTOR INTEGRATED CIRCUIT 未知
公开(公告)号：DE3378662D1
公开(公告)日：1989-01-12
申请号：DE3378662
申请日：1983-12-09
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： HORI RYOICHI , ITOH KIYOO , TANAKA HITOSHI
IPC分类号： H01L27/04 , G01R31/30 , G05F1/46 , G05F3/24 , G11C5/14 , G11C11/407 , H01L21/822 , H01L27/02 , H01L27/06
摘要： A voltage converter is disposed in a semiconductor integrated circuit so as to lower an external supply voltage (VCC) and to feed the lowered voltage (VL) to a partial circuit of the integrated circuit. The voltage converter is constructed so as to produce an output voltage (VL) suited to ordinary operation in the ordinary operation state of the semiconductor integrated circuit and an aging voltage in the aging test of the circuit.

7. 发明专利

DE3279013D1 SEMICONDUCTOR INTEGRATED CIRCUIT 未知
公开(公告)号：DE3279013D1
公开(公告)日：1988-10-13
申请号：DE3279013
申请日：1982-04-16
申请人： HITACHI LTD
发明人： ITOH KIYOO , HORI RYOICHI
IPC分类号： G05F1/46 , G11C5/14 , G11C11/4074 , H01L27/02 , H01L27/08
摘要： A semiconductor memory has a circuit (40) including a memory array (MA) and direct peripheral circuits (SA, PC, XD, YD); and an indirect peripheral circuit (50, 50A). The transistors of the circuit (40) are made smaller than those of the circuit (50, 50A) in order to increase the density of integration, and are fed from a generator (30) with a lower supply voltage (VDP) than the chip supply voltage (Vcc) since their breakdown voltages are also lower. The circuit (50, 50A) receives external signals varying in the range of the higher supply voltage (Vcc) and supplies signals to the circuit (40) which vary in the range of the lower supply voltage (VDP).

8. 发明专利

CA1173519A SEMICONDUCTOR INTEGRATED CIRCUIT 未知
公开(公告)号：CA1173519A
公开(公告)日：1984-08-28
申请号：CA401238
申请日：1982-04-19
申请人： HITACHI LTD
发明人： ITOH KIYOO , HORI RYOICHI
IPC分类号： G05F1/46 , G11C5/14 , G11C11/4074 , H01L27/02 , H03K17/687 , H01L27/06
摘要： : A semiconductor integrated circuit for use as a highly dense memory comprises a first circuit receptive to a first power source voltage for generating a predetermined second power source voltage lower than the first power source voltage. There is also a second circuit receptive to the first power source voltage for generating a second pulse signal for use with the second power source voltage in response to a first pulse signal that varies within the same voltage range as that of the first power source voltage. A third circuit receptive to the second power source voltage and responsive to the second pulse signal has circuit elements of smaller size than those of the first circuit. This arrangement enables very dense packing of the elements while avoiding a need to reduce the voltage that can be applied to avoid risk of dielectric breakdown.

9. 发明专利

DE3650613D1 未知
公开(公告)号：DE3650613D1
公开(公告)日：1997-05-22
申请号：DE3650613
申请日：1986-11-12
申请人： HITACHI LTD
发明人： KITSUKAWA GORO , ITOH KIYOO , HORI RYOICHI , WATANABE TAKAO , SHIMOHIGASHI KATSUHIRO , HOMMA NORIYUKI
IPC分类号： H01L21/761 , H01L21/76 , H01L21/8238 , H01L21/8249 , H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L27/08 , H01L29/78
摘要： The device has a buried layer under a memory array (1120) and arranged between a substrate and a semiconductor layer. A region is formed in the semiconductor layer between the array and a bipolar transistor. The region contacts the buried layer and extends up to main surface of the semiconductor layer. Another buried layer is provided under the bipolar transistor, and arranged between the semiconductor substrate and layer. The memory array on the main surface of a semiconductor layer has a number of memory cells each with a metal insulated semiconductor field effect transistor (MISFET) and a capacitor. The former buried layer is of same conductivity type as that of the semiconductor substrate and impurity concentration higher than that of the semiconductor substrate. Another buried layer has the same conductivity type as that of the semiconductor region.

10. 发明专利

DE3688222T2 未知
公开(公告)号：DE3688222T2
公开(公告)日：1993-11-04
申请号：DE3688222
申请日：1986-07-10
申请人： HITACHI LTD
发明人： WATANABE TAKAO , KITUKAWA GORO , HORI RYOICHI , ITOH KIYOO , KAWAJIRI YOSHIKI , KAWAHARA TAKAYUKI
IPC分类号： G11C7/12 , G11C8/10 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/017 , H03K19/0175 , H03K19/0944 , H03K5/02 , H03K19/08 , H03K19/01 , H03K19/096 , G11C7/00
摘要： A semiconductor device of high integration density and low power consumption prevents the influence of the amplitude of an input signal upon the amplitude of an output signal in such a way that a preceding circuit (C) and a succeeding circuit (D) are endowed with different reference voltages.In an aspect of performance, the semiconductor device is constructed of a circuit which includes a bipolar transistor (26) and an insulated-gate field effect transistor (25, 27, 291, and which operates with reference to one or more voltages (B1), at least one of the reference voltages having a voltage value different from a reference operating voltage (VA) of a preceding circuit (CI which controls the above circuit.In another aspect of performance, first switching means is interposed between a first reference voltage and an input node of a driver circuit, and second switching means is interposed between an output of a preceding circuit and the input of the driver circuit, so that when an output signal of the preceding circuit is at a high level, the second switch is turned "on" while the first switch is turned "off" thereby to produce a still higher potential, and that when the output signal of the preceding circuit is at a low level, the second switch is turned "off" while the first switch is turned "on".The semiconductor device is suited to those circuits of a high-density DRAM and SRAM which use voltage limiters.

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