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71. 发明专利

JPS60110026A LOGICAL CIRCUIT 失效
公开(公告)号：JPS60110026A
公开(公告)日：1985-06-15
申请号：JP21772283
申请日：1983-11-21
申请人： HITACHI LTD
发明人： HAGIWARA YOSHIMUNE , NAKAMURA HIDEO , TAKAGI KATSUAKI , NOGUCHI YOSHIKI , NISHIMUKAI TADAHIKO
IPC分类号： G06F7/00 , G06F1/06 , G06F1/12 , H03K5/156
摘要： PURPOSE:To attain the use of an overlap clock by inserting an intermediate buffer register between an arithmetic circuit and registers provided at the input and the output of said arithmetic circuit. CONSTITUTION:For a microcomputer, intermediate buffer registers 19-21 are set among registers 5 and 6 provided at the input side of an arithmetic circuit 7, an accumulator 8 set at the output side of the circuit 7 and said circuit 7 respectively. The registers 5 and 6 and a bus are driven by a clock phi3, and registers 19 and 20 are driven by a clock phi4 whose pulse width overlaps the clock phi3 by half. Therefore the circuit 7 calculates the data latched by the clock phi3 by the clock phi4 at a point delayed by half of the pulse width. This arithmetic output is fetched by the register 21 and the accumulator 8 with clocks obtained by inverting clocks phi3 and phi4.

72. 发明专利

JPS6035784A VIDEO DISPLAY SYSTEM 失效
公开(公告)号：JPS6035784A
公开(公告)日：1985-02-23
申请号：JP8178284
申请日：1984-04-25
申请人： HITACHI LTD
发明人： WATANABE KAZUO , NAKAMURA HIDEO , ISHIKAWA YASUYO , HAGIWARA YOSHIMUNE
IPC分类号： G09G5/02 , G06F3/14 , G09G1/02 , G09G1/28 , G09G5/00 , G09G5/393 , G09G5/395 , G09G5/397 , G09G5/399

73. 发明专利

JPS6035782A INTEGRATED CIRCUIT MEMORY 失效
公开(公告)号：JPS6035782A
公开(公告)日：1985-02-23
申请号：JP2851184
申请日：1984-02-20
申请人： HITACHI LTD
发明人： ISHIKAWA YASUYO , WATANABE KAZUO , NAKAMURA HIDEO , HAGIWARA YOSHIMUNE
IPC分类号： G06F3/14 , G09G1/00

74. 发明专利

JPS5955621A Converting circuit signal 失效
标题翻译：转换电路信号
公开(公告)号：JPS5955621A
公开(公告)日：1984-03-30
申请号：JP16491282
申请日：1982-09-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OGAWA KAZUYOSHI , TSUKADA TOSHIROU , TAKAGI KATSUAKI , KIDA YUUZOU , HAGIWARA YOSHIMUNE
IPC分类号： H03K7/08 , H03K5/24
CPC分类号： H03K5/24
摘要： PURPOSE:To make uniform offset voltage caused by a temperature change by the 1st and 2nd voltage comparators by constituting both voltage comparators by the same monolithic ICs and arranging these comparators close to each other. CONSTITUTION:The voltage comparators OP4, OP5 receive a positive analog signal e1 and a negative analog signal -e1 by regarding a triangular signal No formed by a triangular wave oscillating circuit OSC as a reference signal. The output signals N3, N4 of the voltage comparators OP4, OP5 are transmitted to the inputs of an AND gate G respectively. A signal OUT having pulse width proportional to the voltage values of e1, -e1 is outputted from the AND gate G. In order to generate offset voltages similarly, the voltage comparators OP4, OP5 are formed on the same semiconductor chip.
摘要翻译：目的：通过由同一单片IC构成两个电压比较器并使这些比较器彼此靠近，使第一和第二电压比较器由温度变化引起的均匀偏移电压。构成：电压比较器OP4，OP5通过将由三角波振荡电路OSC形成的三角形信号No作为参考信号来接收正模拟信号e1和负模拟信号-e1。电压比较器OP4，OP5的输出信号N3，N4分别被发送到与门G的输入。从与门G输出具有与e1，-e1的电压值成比例的脉冲宽度的信号OUT。为了类似地产生偏移电压，电压比较器OP4，OP5形成在同一半导体芯片上。

75. 发明专利

JPS5922170A Temperature compensation system of integrator 失效
标题翻译：整合器温度补偿系统
公开(公告)号：JPS5922170A
公开(公告)日：1984-02-04
申请号：JP13033582
申请日：1982-07-28
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KIDA YUUZOU , TAKAGI KATSUAKI , HAGIWARA YOSHIMUNE , TORII SHIYUUICHI , OGAWA KAZUYOSHI
IPC分类号： G01R22/00 , G01R21/127 , G06G7/18 , G06G7/186
CPC分类号： G06G7/18
摘要： PURPOSE:To correct an arithmetic error resulting from temperature fluctuations, by normalizing the time constant of the integrator of an arithmetic system on the basis of the time constant of the integrator of an LSI-implemented control system. CONSTITUTION:In an electronic (LSI-implemented) watthour meter, a constant- time counting circuit which counts a constant time tau based upon the frequency fDELTA of a triangular wave at room temperature or constant temperature outputs pulses at intervals of time tau to count and store the frequency fDELTA at intervals of time tau to a register, and the normalized count value of time tau is normally 1.0. Similarly, another counter counts output pulses fx corresponding to electric energy for the time tau, and the counted value is stored in the register. Then, the count value of electric energy pulses fx is divided by the count value of the frequency fDELTA at intervals of time tau to remove the time constant CR components of the integrators for generating respective frequencies which vary with temperature, obtaining temperature-compensated electric energy pulses f'x.
摘要翻译：目的：通过根据LSI实现的控制系统的积分器的时间常数对运算系统的积分器的时间常数进行归一化，来校正由于温度波动引起的算术误差。构成：在电子（LSI实现的）电度表中，根据室温或恒温下三角波的频率fDELTA对恒定时间τ进行计数的定时计数电路以时间间隔τ输出脉冲以计数和将频率fDELTA以时间τ的间隔存储到寄存器，并且时间τ的归一化计数值通常为1.0。类似地，另一个计数器计数对应于时间τ的电能的输出脉冲fx，并且计数值被存储在寄存器中。然后，将电能脉冲fx的计数值除以时间间隔τ的频率fDELTA的计数值，以去除用于产生随温度变化的各个频率的积分器的时间常数CR分量，获得温度补偿电能脉冲f'x。

76. 发明专利

JPS5843907B2 失效
公开(公告)号：JPS5843907B2
公开(公告)日：1983-09-29
申请号：JP11351280
申请日：1980-08-20
申请人： HITACHI LTD
发明人： MINATO OSAMU , MASUHARA TOSHIAKI , SAKAI YOSHIO , SHIMOHIGASHI KATSUHIRO , MASUDA HIROO , SUNAMI HIDEO , KAMIGAKI YOSHIAKI , TAKEDA EIJI , HAGIWARA YOSHIMUNE
IPC分类号： G11C17/00 , H01L21/3205 , H01L21/768 , H01L21/82 , H01L23/52

77. 发明专利

JPS5776633A Signal processor 失效
标题翻译：信号处理器
公开(公告)号：JPS5776633A
公开(公告)日：1982-05-13
申请号：JP15205280
申请日：1980-10-31
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： SUGIYAMA SHIZUO , HAGIWARA YOSHIMUNE , MAEDA SHIGEMICHI , AKAZAWA TAKASHI , KOBAYASHI SEIJI , KITA YASUHIRO , KIDA YUUZOU
IPC分类号： G06F3/05 , G06F5/00 , G06F5/01 , G06F17/10
CPC分类号： G06F5/017
摘要： PURPOSE:To eliminate the limitations of the bit length and bit arrangement of an input signal by arranging the bits of the input signal inversely of the bit arrangement inputted to a shift register when the least significant digit bit arrives as an initial bit. CONSTITUTION:When the least significant digit bit LSB comes first, an AND circuit 206 is selected by a control signal 22. Input data stored in a shift register 209 with the LSB at the beginning is transmitted to a data bus output switching circuit 210. When the data is outputted to a line 25, the control signal 22 permits switching so that the 2 of the data bus 25 is assigned to the bit SR15 of the register, and the 2 to the bit SRO. When the most significant digit bit MSB comes first, an AND circuit 205 is signified and the input data is stored in the shift register 209 being shifted successively from the SRO to SR15. In this case, a bus output switching circuit 210 sends the output, as it is, without changing the bit arrangement.
摘要翻译：目的：为了消除输入信号的位长度和位排列的限制，通过将输入信号的位与输入到移位寄存器的比特排列相反，当最低有效位被作为初始位到达时。构成：当最低有效位LSB首先出现时，通过控制信号22选择与电路206.存储在移位寄存器209中的与开始的LSB的输入数据被发送到数据总线输出切换电路210.当数据被输出到行25，控制信号22允许切换，使得数据总线25的2 0被分配给寄存器的位SR15，而2 <15>分配给位SR0。当最高有效位MSB首先出现时，表示AND电路205，并且将输入数据存储在从SRO向SR15连续移位的移位寄存器209中。在这种情况下，总线输出切换电路210原样发送输出，而不改变位的布置。

78. 发明专利

JPS5678167A MANUFACTURE OF COMPLEMENTARYYTYPE INSULATE GATE FIELD EFFECT TRANSISTOR 失效
公开(公告)号：JPS5678167A
公开(公告)日：1981-06-26
申请号：JP15440479
申请日：1979-11-30
申请人： HITACHI LTD
发明人： FUNABASHI TSUNEO , NAKAMURA HIDEO , HAGIWARA YOSHIMUNE , FUKAZAWA SHIGERU , MATSUURA TATSUJI , HARA MICHIO , KIDA YUUZOU
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/78
摘要： PURPOSE:To plan to simplify a manufacturing process by a method wherein double field ions of a P type impurity and double enhancement ions of the P type and N type impurities are injected. CONSTITUTION:An N-well 302 is formed in the P type substrate 301 in low concentration. Then, the P type impurity layer 306 is formed in the substrate 301 in the use of a mask for controlling the impurity concentration. Then again, an impurity having selectively a concentration sloping in the direction of depth is added to a region on which an N type and P type active transistors are formed to form an N type impurity layer 308 lower in concentration than that of the layer 304 and a P type impurity layer 310 lower in concentration than that of the layer 306. By forming the layer 308 and the layer 310 in such a manner, the two masks for controlling the impurity concentration are disused and the manufacturing process can be simplified.

79. 发明专利

JPS5650531A SEMICONDUCTOR INTEGRATED CIRCUIT AND PROGRAMMING METHOD THEREFOR 失效
公开(公告)号：JPS5650531A
公开(公告)日：1981-05-07
申请号：JP12540479
申请日：1979-10-01
申请人： HITACHI LTD
发明人： MASUHARA TOSHIAKI , MINATO OSAMU , SHIMOHIGASHI KATSUHIRO , MASUDA HIROO , SUNAMI HIDEO , SAKAI YOSHIO , KAMIGAKI YOSHIAKI , TAKEDA EIJI , HAGIWARA YOSHIMUNE
IPC分类号： G11C17/00 , G11C17/06 , H01L21/768 , H01L21/82
摘要： PURPOSE:To facilitate the modification of circuit constitution by providing a wiring layer for programming a circuit comprising a semiconductor layer wherein two low resistance parts oppose each other with a high resistance part being provided in- between on an insulating film on the surface of a semiconductor substrate, and reducing the resistance of the high resistance part. CONSTITUTION:On an SiO2 layer 8 on the surface of an Si substrate 9, n type polycrystal layers 5 and 7 are arranged so that they oppose each other with a high resistance polycrystal Si layer 6 being provided in-between, thereby a wiring for programming is constituted. Diffusion is performed from the n type low resistance layers 5 and 7 by irradiating a laser spot or an electron beam spot and giving the energy, thereby the high resistance layer 6 is converted into low resistance layer 11. In this method, the n type layers 5 and 7 which have been in the nonconductive state before irradiation become the conductive state after the irradiation, and the programming wiring under the nonactive state becomes the active state. Therefore, the programmable IC can be readily formed, and ROMs, programmable logic arrays and the like can be readily constituted.

80. 发明专利

JPS5534507A ELECTRONIC TUNING TELEVISION PICTURE RECEIVER 失效
公开(公告)号：JPS5534507A
公开(公告)日：1980-03-11
申请号：JP10621278
申请日：1978-09-01
申请人： HITACHI LTD
发明人： HAGIWARA YOSHIMUNE , SAWASE TERUMI , TAKAI ATSUSHI , KIDA YUUZOU , HONDA AKIRA
IPC分类号： H03J5/02
摘要： PURPOSE:To eliminate the effect due to the characteristic change of the variable capacity diode by increasing or decreasing the data in a fixed ratio for the tuning voltage read out from the memory device. CONSTITUTION:The following component units are provided: tuning circuit 2 the local oscillation frequency of which receives a variable control by the application voltage to the variable capacity diode; input means 7 to designate the selecting channel; memory means 9 memorizing the digital data showing the tuning voltage to be applied every channel; means 8 to read out the voltage data corresponding to the channel designated by means 7 from means 9; D/A converter 11 to convert the voltage data read out into the analog signal to be applied to the variable capacity diode; and tuning control means 10 to vary the voltage data read out from means 9 with a fixed rate until it reaches the tuning point and then to supply it to D/A converter 11.

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