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71. 发明申请

US20050199966A1 Dual work function semiconductor structure with borderless contact and method of fabricating the same 失效
标题翻译：具有无边界接触的双功能半导体结构及其制造方法
公开(公告)号：US20050199966A1
公开(公告)日：2005-09-15
申请号：US11098103
申请日：2005-04-04
申请人： Qiuyi Ye , William Tonti , Yujun Li
发明人： Qiuyi Ye , William Tonti , Yujun Li
IPC分类号： H01L21/28 , H01L21/60 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8242 , H01L23/522 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/423 , H01L29/43 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10894
摘要： A dual work function semiconductor structure with borderless contact and method of fabricating the same are presented. The structure may include a field effect transistor (FET) having a substantially cap-free gate and a conductive contact to a diffusion adjacent to the cap-free gate, wherein the conductive contact is borderless to the gate. Because the structure is a dual work function structure, the conductive contact is allowed to extend over the cap-free gate without being electrically connected thereto.
摘要翻译：提出了一种具有无边界接触的双功能半导体结构及其制造方法。该结构可以包括具有基本无帽栅极的场效应晶体管（FET）和与无盖栅极相邻的扩散部的导电接触，其中导电触点与栅极无边界。由于该结构是双重功能结构，所以允许导电接触件在无盖栅极上延伸而不与其电连接。

72. 发明授权

US08575718B2 Programmable electrical fuse 失效
标题翻译：可编程电气保险丝
公开(公告)号：US08575718B2
公开(公告)日：2013-11-05
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, Jr. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/52 , H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

73. 发明申请

US20120280356A1 UNIFORMLY ALIGNED WELL AND ISOLATION REGIONS IN A SUBSTRATE AND RESULTING STRUCTURE 审中-公开
标题翻译：在基板和结构结构中均匀分布的井和隔离区
公开(公告)号：US20120280356A1
公开(公告)日：2012-11-08
申请号：US13552695
申请日：2012-07-19
申请人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
发明人： Wagdi W. Abadeer , Lilian Kamal , Kiran V. Chatty , Robert J. Gauthier, JR. , Jed H. Rankin , Robert R. Robison , William Tonti
IPC分类号： H01L29/06
CPC分类号： H01L21/76232
摘要： A solution for alleviating variable parasitic bipolar leakages in scaled semiconductor technologies is described herein. Placement variation is eliminated for edges of implants under shallow trench isolation (STI) areas by creating a barrier to shield areas from implantation more precisely than with only a standard photolithographic mask. An annealing process expands the implanted regions such their boundaries align within a predetermined distance from the edge of a trench. The distances are proportionate for each trench and each adjacent isolation region.
摘要翻译：本文描述了用于减小缩放半导体技术中的可变寄生双极性泄漏的解决方案。在浅沟槽隔离（STI）区域下的植入物的边缘，通过与仅使用标准光刻掩模相比更加精确地产生屏蔽区域而不是植入屏蔽区域来消除放置变化。退火处理使注入区域扩展，使其边界在与沟槽边缘预定距离内对齐。距离对于每个沟槽和每个相邻的隔离区域是成比例的。

74. 发明申请

US20120049321A1 PROGRAMMABLE ELECTRICAL FUSE 失效
标题翻译：可编程电气保险丝
公开(公告)号：US20120049321A1
公开(公告)日：2012-03-01
申请号：US13289529
申请日：2011-11-04
申请人： Michael J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
发明人： Michael J. Abou-Khalil , Robert J. Gauthier, JR. , Tom C. Lee , Junjun Li , Souvick Mitra , Christopher S. Putnam , William Tonti
IPC分类号： H01L23/525 , H01L21/326
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to e-fuse devices, and more particularly to a device and method of forming an e-fuse device, the method comprising providing a first conductive layer connected to a second conductive layer, the first and second conductive layers separated by a barrier layer having a first diffusivity different than a second diffusivity of the first conductive layer. A void is created in the first conductive layer by driving an electrical current through the e-fuse device.
摘要翻译：本发明涉及电熔丝装置，更具体地说，涉及一种形成电熔丝装置的装置和方法，所述方法包括提供连接到第二导电层的第一导电层，所述第一和第二导电层由阻挡层具有与第一导电层的第二扩散率不同的第一扩散率。通过驱动电流通过电熔丝装置而在第一导电层中产生空隙。

75. 发明授权

US07772649B2 SOI field effect transistor with a back gate for modulating a floating body 失效
标题翻译：具有用于调制浮体的背栅的SOI场效应晶体管
公开(公告)号：US07772649B2
公开(公告)日：2010-08-10
申请号：US12036325
申请日：2008-02-25
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , Carl Radens , William Tonti
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/42384 , H01L29/66772 , H01L29/78612 , H01L29/78648
摘要： A masking layer is applied over a top semiconductor layer and patterned to expose in an opening a shallow trench isolation structure and a portion of a top semiconductor region within which a first source/drain region and a body is to be formed. Ions are implanted into a portion of a buried insulator layer within the area of the opening to form damaged buried insulator region. The shallow trench isolation structure is removed and the damaged buried insulator region is etched selective to undamaged buried insulator portions to form a cavity. A dielectric layer is formed on the sidewalls and the exposed bottom surface of the top semiconductor region and a back gate filling the cavity is formed. A contact is formed to provide an electrical bias to the back gate so that the electrical potential of the body and the first source/drain region is electrically modulated.
摘要翻译：将掩模层施加在顶部半导体层上并且被图案化以在开口中暴露浅沟槽隔离结构以及要在其中形成第一源极/漏极区域和主体的顶部半导体区域的一部分。将离子注入到开口区域内的埋入绝缘体层的一部分中以形成损坏的埋层绝缘体区域。去除浅沟槽隔离结构，并且损坏的埋层绝缘体区域被选择性地蚀刻到未损坏的埋入绝缘体部分以形成空腔。在顶部半导体区域的侧壁和暴露的底表面上形成介电层，并且形成填充空腔的背栅。形成接触以向后栅极提供电偏压，使得主体和第一源极/漏极区域的电势被电调制。

76. 发明申请

US20090072290A1 SOI CMOS COMPATIBLE MULTIPLANAR CAPACITOR 有权
标题翻译： SOI CMOS兼容多元电容器
公开(公告)号：US20090072290A1
公开(公告)日：2009-03-19
申请号：US11857770
申请日：2007-09-19
申请人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , William Tonti
发明人： Kangguo Cheng , Louis C. Hsu , Jack A. Mandelman , William Tonti
IPC分类号： H01L21/70 , H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/0629 , H01L27/10861 , H01L28/60
摘要： An isolated shallow trench isolation portion is formed in a top semiconductor portion of a semiconductor-on-insulator substrate along with a shallow trench isolation structure. A trench in the shape of a ring is formed around a doped top semiconductor portion and filled with a conductive material such as doped polysilicon. The isolated shallow trench isolation portion and the portion of a buried insulator layer bounded by a ring of the conductive material are etched to form a cavity. A capacitor dielectric is formed on exposed semiconductor surfaces within the cavity and above the doped top semiconductor portion. A conductive material portion formed in the trench and above the doped top semiconductor portion constitutes an inner electrode of a capacitor, while the ring of the conductive material, the doped top semiconductor portion, and a portion of a handle substrate abutting the capacitor dielectric constitute a second electrode.
摘要翻译：孤立的浅沟槽隔离部分形成在绝缘体上半导体衬底的顶部半导体部分以及浅沟槽隔离结构中。环形形状的沟槽形成在掺杂顶部半导体部分周围，并填充有诸如掺杂多晶硅的导电材料。隔离的浅沟槽隔离部分和由导电材料的环限定的掩埋绝缘体层的部分被蚀刻以形成空腔。在空腔内的暴露的半导体表面上和掺杂的顶部半导体部分之上形成电容器电介质。形成在沟槽中并且在掺杂顶部半导体部分上方的导电材料部分构成电容器的内部电极，而导电材料的环，掺杂的顶部半导体部分和与电容器电介质邻接的手柄衬底的一部分构成一个第二电极。

77. 发明授权

US07462547B2 Method of fabricating a bipolar transistor having reduced collector-base capacitance 失效
标题翻译：制造具有减小的集电极 - 基极电容的双极晶体管的方法
公开(公告)号：US07462547B2
公开(公告)日：2008-12-09
申请号：US11633380
申请日：2006-12-04
申请人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
发明人： Hiroyuki Akatsu , Rama Divakaruni , Marwan Khater , Christopher M. Schnabel , William Tonti
IPC分类号： H01L21/331 , H01L27/082
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0692 , H01L29/0821
摘要： A method is provided for fabricating a bipolar transistor that includes growing an epitaxial layer onto an underlaying region having a low dopant concentration and a trench isolation region defining the edges of an active region layer, implanting a portion of the epitaxial layer through a mask to define a collector region having a relatively high dopant concentration, the collector region laterally adjoining a second region of the epitaxial layer having the low dopant concentration; forming an intrinsic base layer overlying the collector region and the second region, the intrinsic base layer including an epitaxial region in conductive communication with the collector region; forming a low-capacitance region laterally separated from the collector region by the second region, the low-capacitance region including a dielectric region disposed in an undercut directly underlying the intrinsic base layer; and forming an emitter layer overlying the intrinsic base layer.
摘要翻译：提供了一种用于制造双极晶体管的方法，该双极晶体管包括将外延层生长到具有低掺杂剂浓度的衬底区域和限定有源区域层的边缘的沟槽隔离区域，通过掩模注入外延层的一部分以限定具有相对较高掺杂剂浓度的集电极区域，所述集电极区域横向邻接所述外延层的具有低掺杂浓度的第二区域; 形成覆盖所述集电极区域和所述第二区域的本征基极层，所述本征基极层包括与所述集电极区域导通连通的外延区域; 形成由所述第二区域与所述集电极区域横向分离的低电容区域，所述低电容区域包括设置在所述本征基极层下方的底切处的电介质区域; 并形成覆盖本征基层的发射极层。

78. 发明申请

US20060252226A1 Integrated SOI fingered decoupling capacitor 失效
公开(公告)号：US20060252226A1
公开(公告)日：2006-11-09
申请号：US11485599
申请日：2006-07-12
申请人： Zarchary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
发明人： Zarchary Berndlmaier , Edward Kiewra , Carl Radens , William Tonti
IPC分类号： H01L21/76
CPC分类号： H01L29/66181 , H01L21/84 , H01L27/0629 , H01L27/0805 , H01L27/1087 , H01L27/1203
摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

79. 发明申请

US20060249799A1 Concurrent fin-fet and thick body device fabrication 有权
公开(公告)号：US20060249799A1
公开(公告)日：2006-11-09
申请号：US11481120
申请日：2006-07-05
申请人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
发明人： Wagdi Abadeer , Jeffrey Brown , David Fried , Robert Gauther , Edward Nowak , Jed Rankio , William Tonti
IPC分类号： H01L29/76
CPC分类号： H01L29/786 , H01L21/845 , H01L27/1211 , H01L29/4908 , H01L29/78615
摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

80. 发明申请

US20060128071A1 Integrated antifuse structure for finfet and cmos devices 有权
标题翻译： Finf集成反熔丝结构和cmos器件
公开(公告)号：US20060128071A1
公开(公告)日：2006-06-15
申请号：US10539333
申请日：2002-12-20
申请人： Jed Rankin , Wagdl Abadeer , Jeffrey Brown , William Tonti
发明人： Jed Rankin , Wagdl Abadeer , Jeffrey Brown , William Tonti
IPC分类号： H01L21/82
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/785
摘要： A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).
摘要翻译：描述了与半导体器件（例如FINFET或平面CMOS器件）集成的制造和反熔丝结构（100）的方法。设置在设置在基板（10）上的绝缘体（3）上的半导体材料（11）的区域; 蚀刻工艺暴露了半导体材料中的多个拐角（111-114）。露出的角部被氧化，以形成角落处的细长尖端（111t-114t）; 去除顶部上方的氧化物（31）。然后在半导体材料上形成氧化物层（例如栅极氧化物），并覆盖在角部上; 该层在拐角处具有减小的厚度。在角部处形成与氧化物层（51）接触的导电材料层（60），从而通过氧化物层在半导体材料和导电材料层之间形成多个可能的击穿路径。将诸如老化电压的电压施加到结构将至少一个击穿路径转换成导电路径（103,280）。

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