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71. 发明授权

US06251744B1 Implant method to improve characteristics of high voltage isolation and high voltage breakdown 有权
标题翻译：植入法提高高压隔离和高压击穿特性
公开(公告)号：US06251744B1
公开(公告)日：2001-06-26
申请号：US09356870
申请日：1999-07-19
申请人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
发明人： Hung-Der Su , Chrong-Jung Lin , Jong Chen , Wen-Ting Chu , Hung-Cheng Sung , Di-Son Kuo
IPC分类号： H01L2176
CPC分类号： H01L21/76213
摘要： A layer of well oxide is grown over the n-well or p-well region of the semiconductor substrate. A deep n-well implant is performed in high voltage device region, followed by a deep n-well drive-in of the deep n-well implant. The well oxide is removed; the field oxide (FOX) region is created in the high voltage device region. A layer of sacrificial oxide is deposited on the surface of the semiconductor substrate. A low voltage cluster n-well implant is performed in the high voltage PMOS region of the semiconductor substrate followed, for the high voltage NMOS region, by a low voltage cluster p-well implant which is followed by a buried p-well cluster implant.
摘要翻译：在半导体衬底的n阱或p阱区域上生长一层良好的氧化物。在高电压器件区域中进行深n阱注入，随后是深n阱注入的深n阱驱动。去除氧化物; 在高电压器件区域中产生场氧化物（FOX）区域。牺牲氧化物层沉积在半导体衬底的表面上。在半导体衬底的高电压PMOS区域中执行低电压簇n阱注入，随后是高压NMOS区，由低电压簇p阱注入，随后是埋置的p阱簇注入。

72. 发明授权

US06455887B1 Nonvolatile devices with P-channel EEPROM device as injector 有权
标题翻译：具有P通道EEPROM器件的非易失性器件作为注入器
公开(公告)号：US06455887B1
公开(公告)日：2002-09-24
申请号：US09320754
申请日：1999-05-27
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/045 , H01L27/115 , H01L29/7885
摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.
摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。宽栅电极EEPROM堆叠桥接N区和P区中的沟道。堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。在与栅电极堆叠自对准的P区的表面中形成N +漏极区。在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

73. 发明授权

US6060360A Method of manufacture of P-channel EEprom and flash EEprom devices 失效
标题翻译： P通道EEprom和闪存EEprom器件的制造方法
公开(公告)号：US6060360A
公开(公告)日：2000-05-09
申请号：US843183
申请日：1997-04-14
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/788 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
摘要翻译：在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅宽度。在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

74. 发明授权

US5933732A Nonvolatile devices with P-channel EEPROM devices as injector 失效
标题翻译：具有P通道EEPROM器件的非易失性器件作为注入器
公开(公告)号：US5933732A
公开(公告)日：1999-08-03
申请号：US851563
申请日：1997-05-07
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/045 , H01L27/115 , H01L29/7885
摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.
摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。宽栅电极EEPROM堆叠桥接N区和P区中的沟道。堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。在与栅电极堆叠自对准的P区的表面中形成N +漏极区。在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

75. 发明授权

US06509603B2 P-channel EEPROM and flash EEPROM devices 有权
标题翻译： P通道EEPROM和闪存EEPROM器件
公开(公告)号：US06509603B2
公开(公告)日：2003-01-21
申请号：US09818296
申请日：2001-03-27
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
IPC分类号： H01L29788
CPC分类号： H01L29/42324 , H01L29/7885
摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
摘要翻译：在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅宽度。在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

76. 发明授权

US06246089B1 P-channel EEPROM devices 有权
标题翻译： P通道EEPROM器件
公开(公告)号：US06246089B1
公开(公告)日：2001-06-12
申请号：US09524518
申请日：2000-03-13
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
摘要翻译：在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅宽度。在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

77. 发明授权

US5970341A Method for forming vertical channels in split-gate flash memory cell 失效
标题翻译：分闸式闪存单元形成垂直通道的方法
公开(公告)号：US5970341A
公开(公告)日：1999-10-19
申请号：US988772
申请日：1997-12-11
申请人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
发明人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole. Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
摘要翻译：通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。衬底中的源极/漏极区域与浮栅电极层自对准。通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图。在其中形成控制门孔。在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

78. 发明授权

US6133097A Method for forming mirror image split gate flash memory devices by forming a central source line slot 有权
标题翻译：通过形成中心源线槽来形成镜像分离门闪存器件的方法
公开(公告)号：US6133097A
公开(公告)日：2000-10-17
申请号：US133969
申请日：1998-08-14
申请人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。栅电极中心的图案源极线槽向下堆叠到衬底。在源线插槽的底部形成源区。在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。形成自对准漏极区。

79. 发明授权

US6078076A Vertical channels in split-gate flash memory cell 有权
标题翻译：分闸式闪存单元中的垂直通道
公开(公告)号：US6078076A
公开(公告)日：2000-06-20
申请号：US317645
申请日：1999-05-24
申请人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
发明人： Chrong-Jung Lin , Chia-Ta Hsieh , Jong Chen , Di-Son Kuo
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L29/42336 , H01L29/66825 , H01L29/7883
摘要： A method of forming a vertical memory split gate flash memory device on a silicon semiconductor substrate is provided by the following steps. Form a floating gate trench hole in the silicon semiconductor substrate, the trench hole having trench surfaces. Form a tunnel oxide layer on the trench surfaces, the tunnel oxide layer having outer surfaces. Form a floating gate electrode layer filling the trench hole on the outer surfaces of the tunnel oxide layer. Form source/drain regions in the substrate self-aligned with the floating gate electrode layer. Pattern the floating gate electrode layer by removing the gate electrode layer from the drain region side of the trench hole Form a control gate hole therein. Form an interelectrode dielectric layer over the top surface of the floating gate electrode, and over the tunnel oxide layer. Form a control gate electrode over the interelectrode dielectric layer over the top surface of the floating gate electrode and extending down into the control gate hole in the trench hole.
摘要翻译：通过以下步骤提供在硅半导体衬底上形成垂直存储器分离栅极闪存器件的方法。在硅半导体衬底中形成浮栅沟槽，沟槽具有沟槽表面。在沟槽表面上形成隧道氧化物层，隧道氧化物层具有外表面。形成填充隧道氧化物层的外表面上的沟槽的浮栅电极层。衬底中的源极/漏极区域与浮栅电极层自对准。通过从沟槽的漏极区域侧去除栅极电极层来对浮栅电极层进行构图在其中形成控制栅极孔。在浮栅电极的顶表面上方，并在隧道氧化物层之上形成电极间电介质层。在浮栅电极的顶表面上方的电极间电介质层上形成控制栅电极，并向下延伸到沟槽孔中的控制栅极孔。

80. 发明授权

US06326662B1 Split gate flash memory device with source line 有权
标题翻译：分流闸闪存器件与源极线
公开(公告)号：US06326662B1
公开(公告)日：2001-12-04
申请号：US09633643
申请日：2000-08-07
申请人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
发明人： Chia-Ta Hsieh , Chrong Jung Lin , Shui-Hung Chen , Di-Son Kuo
IPC分类号： H01L29788
CPC分类号： H01L27/11519 , H01L27/115 , H01L27/11521
摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.
摘要翻译：形成分离栅电极MOSFET器件的方法包括以下步骤。在半导体衬底上形成隧道氧化层。在隧道氧化物层上形成浮栅电极层。在浮栅电极层上形成掩蔽帽。掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。栅电极中心的图案源极线槽向下堆叠到衬底。在源线插槽的底部形成源区。在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。形成自对准漏极区。

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