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1. 发明授权

US6060360A Method of manufacture of P-channel EEprom and flash EEprom devices 失效
标题翻译： P通道EEprom和闪存EEprom器件的制造方法
公开(公告)号：US6060360A
公开(公告)日：2000-05-09
申请号：US843183
申请日：1997-04-14
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/788 , H01L21/8247
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
摘要翻译：在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅宽度。在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

2. 发明授权

US06509603B2 P-channel EEPROM and flash EEPROM devices 有权
标题翻译： P通道EEPROM和闪存EEPROM器件
公开(公告)号：US06509603B2
公开(公告)日：2003-01-21
申请号：US09818296
申请日：2001-03-27
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
IPC分类号： H01L29788
CPC分类号： H01L29/42324 , H01L29/7885
摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
摘要翻译：在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅宽度。在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

3. 发明授权

US06246089B1 P-channel EEPROM devices 有权
标题翻译： P通道EEPROM器件
公开(公告)号：US06246089B1
公开(公告)日：2001-06-12
申请号：US09524518
申请日：2000-03-13
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Juang-Ke Yeh
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324 , H01L29/7885
摘要： A flash EEPROM or split gate flash EEPROM is made on a doped silicon semiconductor N-well formed in a doped semiconductor substrate. A channel with a given width is formed in the N-well which is covered with a tunnel oxide layer, and an N+ doped polysilicon floating gate electrode layer, which can be patterned into a split gate floating gate electrode having a narrower width than the channel width. An interelectrode dielectric layer is formed over the floating gate electrode and the exposed tunnel oxide. A control gate electrode includes a layer composed of P+ doped polysilicon over the interelectrode dielectric layer. The tunnel oxide layer, the floating gate electrode layer, the interelectrode dielectric layer, and the control gate electrode are patterned into a gate electrode stack above the channel. A source region and a drain region are formed in the surface of the substrate with a P type of dopant, the source region and the drain region being self-aligned with the gate electrode stack.
摘要翻译：在掺杂半导体衬底中形成的掺杂硅半导体N阱上制造闪存EEPROM或分离栅极快速EEPROM。具有给定宽度的通道形成在被隧道氧化物层覆盖的N阱中，以及N +掺杂多晶硅浮栅电极层，其可以被图案化成具有比沟道窄的宽度的分离栅极浮栅宽度。在浮栅电极和暴露的隧道氧化物之上形成电极间电介质层。控制栅电极包括由电极间电介质层上的P +掺杂多晶硅构成的层。将隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极图案化成沟道上方的栅电极堆叠。源极区域和漏极区域用P型掺杂剂形成在衬底的表面中，源极区域和漏极区域与栅电极堆叠自对准。

4. 发明授权

US06455887B1 Nonvolatile devices with P-channel EEPROM device as injector 有权
标题翻译：具有P通道EEPROM器件的非易失性器件作为注入器
公开(公告)号：US06455887B1
公开(公告)日：2002-09-24
申请号：US09320754
申请日：1999-05-27
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/045 , H01L27/115 , H01L29/7885
摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.
摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。宽栅电极EEPROM堆叠桥接N区和P区中的沟道。堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。在与栅电极堆叠自对准的P区的表面中形成N +漏极区。在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

5. 发明授权

US5933732A Nonvolatile devices with P-channel EEPROM devices as injector 失效
标题翻译：具有P通道EEPROM器件的非易失性器件作为注入器
公开(公告)号：US5933732A
公开(公告)日：1999-08-03
申请号：US851563
申请日：1997-05-07
申请人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
发明人： Yai-Fen Lin , Shiou-Hann Liaw , Di-Son Kuo , Jian-Hsing Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0441 , G11C16/045 , H01L27/115 , H01L29/7885
摘要： An FET semiconductor device includes an N-region and a P-region formed in the substrate with the N-region juxtaposed with the P-region with an interface between the N-region and the P-region and with a first channel in the N-region and a second channel in the P-region. An N+ drain region is near the interface on one side of the first channel in the P-region. A P+ drain region is near the interface on one side of the second channel in the N-region. An N+ source region is on the opposite side of the first channel from the interface in the P-region. A P+ source region is on the opposite side of the first channel from the interface in the N-region. A wide gate electrode EEPROM stack bridges the channels in the N-region and the P-region. The stack includes a tunnel oxide layer, a floating gate electrode layer, an interelectrode dielectric layer, and a control gate electrode. An N+ drain region is formed in the surface of the P-region self-aligned with the gate electrode stack. A P+ drain region is formed in the surface of the N-region self-aligned with the gate electrode stack.
摘要翻译： FET半导体器件包括形成在衬底中的N区和P区，其中N区与P区并置，具有N区和P区之间的界面，并且N区中的第一通道 - 区域和P区域中的第二个通道。 N +漏极区域位于P区域中第一通道一侧的界面附近。 P +漏极区域位于N区域中第二通道一侧的界面附近。 N +源极区域与第一通道的与P区域中的界面相反。 P +源极区域与N区域中的界面在第一通道的相对侧。宽栅电极EEPROM堆叠桥接N区和P区中的沟道。堆叠包括隧道氧化物层，浮栅电极层，电极间电介质层和控制栅电极。在与栅电极堆叠自对准的P区的表面中形成N +漏极区。在与栅极电极堆叠自对准的N区域的表面中形成P +漏极区域。

6. 发明授权

US06483159B1 Undoped polysilicon as the floating-gate of a split-gate flash cell 有权
标题翻译：未掺杂的多晶硅作为分裂栅极闪存单元的浮栅
公开(公告)号：US06483159B1
公开(公告)日：2002-11-19
申请号：US09617426
申请日：2000-07-14
申请人： Yai-Fen Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Juang-Ke Yeh , Di-Son Kuo
发明人： Yai-Fen Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Juang-Ke Yeh , Di-Son Kuo
IPC分类号： H01L2976
CPC分类号： H01L29/66825 , H01L29/42324
摘要： A split gate EEPROM memory device formed on a doped silicon semi-conductor substrate starting with an initial oxide layer with an undoped first polysilicon layer formed thereon. A polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.
摘要翻译：一种分裂门EEPROM存储器件，形成在掺杂硅半导体衬底上，起始于其上形成有未掺杂的第一多晶硅层的初始氧化物层。在未掺杂的第一多晶硅层上的多晶硅氧化物硬掩模，用于构图初始氧化物层和未掺杂的第一多晶硅层，然后将其从未掺杂的第一多晶硅层和衬底上的初始氧化物层进行蚀刻以形成浮置栅电极堆叠。然后形成隧道氧化物层和掺杂多晶硅并将它们图案化成控制栅极电极堆叠，其中控制栅极电极堆叠相对于浮动栅电极堆叠位于分离栅极配置中。

7. 发明授权

US6121088A Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell 有权
标题翻译：制造未掺杂多晶硅作为分闸栅极浮栅的方法
公开(公告)号：US6121088A
公开(公告)日：2000-09-19
申请号：US156054
申请日：1998-09-17
申请人： Yai-Fen Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Juang-ke Yeh , Di-Son Kuo
发明人： Yai-Fen Lin , Chia-Ta Hsieh , Hung-Cheng Sung , Juang-ke Yeh , Di-Son Kuo
IPC分类号： H01L21/336 , H01L29/423 , H01L21/4763
CPC分类号： H01L29/66825 , H01L29/42324
摘要： Form a split gate EEPROM memory device on a doped silicon semiconductor substrate starting with an initial oxide layer and form an undoped first polysilicon layer thereon. Then form a polysilicon oxide hard mask over the undoped first polysilicon layer for use in patterning the initial oxide layer and the undoped first polysilicon layer which are then etched to form a floating gate electrode stack from the undoped first polysilicon layer and the initial oxide layer on the substrate. Then form a tunnel oxide layer and a doped polysilicon and pattern them into control gate electrode stack, with the control gate electrode stack being located in a split-gate configuration with respect to the floating gate electrode stack.
摘要翻译：在掺杂硅半导体衬底上形成一个分裂栅极EEPROM存储器件，从初始氧化层开始并在其上形成未掺杂的第一多晶硅层。然后在未掺杂的第一多晶硅层上形成多晶硅氧化物硬掩模，用于图案化初始氧化物层和未掺杂的第一多晶硅层，然后将其从未掺杂的第一多晶硅层和初始氧化物层上蚀刻形成浮栅电极堆叠底物。然后形成隧道氧化物层和掺杂多晶硅并将它们图案化成控制栅极电极堆叠，其中控制栅极电极堆叠相对于浮动栅电极堆叠位于分离栅极配置中。

8. 发明授权

US07417278B2 Method to increase coupling ratio of source to floating gate in split-gate flash 有权
标题翻译：提高分流栅闪光时源极与浮栅耦合比的方法
公开(公告)号：US07417278B2
公开(公告)日：2008-08-26
申请号：US11122726
申请日：2005-05-05
申请人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
发明人： Chia-Ta Hsieh , Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Jack Yeh
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/66825 , H01L29/7885
摘要： A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In this manner, a higher coupling ratio is achieved without an increase in the cell size while at the same time alleviating the punchthrough and junction break-down of source region by sharing gate voltage along the side-wall.
摘要翻译：提供具有能够与电池的浮动栅极三维耦合的三维源的分裂栅极闪存单元及其形成方法。这是通过首先形成隔离沟槽，用共形氧化物衬里，然后用隔离氧化物填充，然后对其进行蚀刻，以在沟槽的上部形成三维耦合区域。接下来通过用多晶硅填充沟槽的三维区域并对其进行蚀刻来形成浮栅。控制栅极通过中间多晶硅氧化物形成在浮动栅上。浮栅形成延伸到沟槽的三维耦合区域中的支腿，从而提供与源也呈三维区域的三维耦合。形成第三维的浮动栅的腿或侧壁提供了增加源极和浮动栅极之间的耦合的额外区域。以这种方式，在不增加电池尺寸的同时实现更高的耦合比，同时通过沿着侧壁共享栅极电压来减轻源极区域的穿通和结断流。

9. 发明授权

US06573555B1 Source side injection programming and tip erasing P-channel split gate flash memory cell 有权
标题翻译：源端注入编程和引脚擦除P沟道分离栅极闪存单元
公开(公告)号：US06573555B1
公开(公告)日：2003-06-03
申请号：US09587464
申请日：2000-06-05
申请人： Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Chia-Ta Hsieh
发明人： Yai-Fen Lin , Di-Son Kuo , Hung-Cheng Sung , Chia-Ta Hsieh
IPC分类号： H01L29788
CPC分类号： H01L29/42324 , H01L21/28273
摘要： A split gate P-channel flash memory cell and method of forming a split gate P-channel flash memory cell which avoids of high erasing voltage, reverse tunneling during programming, drain disturb and over erase problems, and permits shrinking the cell dimensions. The control gate has a concave top surface which intersects with the sidewalls to form a sharp edge. The cell is programmed by charging the floating gate with electrons by means of hot electron injection from the channel into the floating gate. The cell is erased by discharging the excess electrons from the floating gate into the control gate using Fowler-Nordheim tunneling. The sharp edge at the intersection of the concave top surface and the sidewalls of the floating gate produces a high electric field between the control gate and the floating gate to accomplish the Fowler-Nordheim tunneling with only moderate voltage differences between the floating gate and control gate. The P-channel flash memory cell has a higher impact ionization rage for creating hot electrons so that the distance between the source and drain junctions and the length of the floating gate can be kept small thereby permitting the dimensions of the flash memory cell to be shrunk.
摘要翻译：分裂门P沟道快闪存储单元以及形成分离栅极P沟道闪存单元的方法，其避免高擦除电压，编程期间的反向隧穿，漏极干扰和过度擦除问题，并且允许缩小单元尺寸。控制门具有与侧壁相交以形成锋利边缘的凹顶表面。通过从通道进入浮动栅极的热电子注入，用电子对浮动栅极充电来对单元进行编程。使用Fowler-Nordheim隧道将多余的电子从浮动栅极放电到控制栅中来消除电池。在凹顶表面和浮动栅极的相交处的尖锐边缘在控制栅极和浮动栅极之间产生高电场，以在浮动栅极和控制栅极之间仅具有适度的电压差来实现Fowler-Nordheim隧道。 P沟道闪速存储单元对于产生热电子具有较高的冲击电离强度，使得源极和漏极结之间的距离和浮置栅极的长度可以保持较小，从而允许闪存单元的尺寸缩小。

10. 发明授权

US06538277B2 Split-gate flash cell 有权
标题翻译：分离式闪存单元
公开(公告)号：US06538277B2
公开(公告)日：2003-03-25
申请号：US09920601
申请日：2001-08-02
申请人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
发明人： Hung-Cheng Sung , Di-Son Kuo , Chuang-Ke Yeh , Chia-Ta Hsieh , Yai-Fen Lin , Wen-Ting Chu
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/76895 , H01L21/76897 , H01L27/115 , H01L29/42324 , H01L29/66825
摘要： A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.
摘要翻译：公开了一种形成分裂栅闪存单元中用于增强的F-N隧穿的第一多晶硅栅尖（多尖端）的新方法。在不使用厚多晶硅层作为浮动栅极的情况下形成多尖端。这可以通过在多晶硅上形成氧化层并氧化多晶硅的侧壁来实现。由于浮栅的多晶硅的起始厚度相对较薄，所以形成的栅极尖或多尖端也必然是薄且尖锐的。因此，该方法避免了超大规模集成技术的缩小设备中遇到的氧化物薄化问题，提高了EEPROM的快速可编程性和擦除性能。

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