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71. 发明授权

US5574756A Method for generating digital communication system clock signals & circuitry for performing that method 失效
标题翻译：用于产生用于执行该方法的数字通信系统时钟信号和电路的方法
公开(公告)号：US5574756A
公开(公告)日：1996-11-12
申请号：US332561
申请日：1994-10-31
申请人： Deog-Kyoon Jeong
发明人： Deog-Kyoon Jeong
IPC分类号： H04L7/04 , H03L7/081 , H03L7/085 , H04L7/033 , H03D3/24
CPC分类号： H03L7/085 , H03L7/0812 , H04L7/0337
摘要： A clock generating circuit generates 2n clocks (where n is a positive integer number) each having 1/2n frequency of a maximum baud rate of data bit-stream input and a phase difference of .pi./n between successive phases thereof, and simultaneously shifts the phases on the clocks ahead or behind until the phases between the clocks and corresponding data bits of the data bit-stream input are locked in quadrature, by comparing the phase of the clock with those of data bit-stream input and adjusting the phases of the clocks.
摘要翻译：时钟发生电路产生2n个数据位流输入的最大波特率的+ E，fra 1/2 + EE n个频率的2n个时钟（n为正整数），连续的并且同时在前面或后面的时钟上移动相位，直到通过将时钟的相位与数据比特流的相位相比较来将数据比特流输入的时钟和相应数据比特之间的相位锁定在正交上输入和调整时钟的相位。

72. 发明授权

US07602253B2 Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：带前馈分频器的自适应带宽锁相环
公开(公告)号：US07602253B2
公开(公告)日：2009-10-13
申请号：US11637254
申请日：2006-12-11
申请人： Jaeha Kim , Deog-Kyoon Jeong
发明人： Jaeha Kim , Deog-Kyoon Jeong
IPC分类号： H03L7/00
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括第一和第二子锁相环（sub-PLL），其包括第一和第二压控振荡器（VCO），以提供第一和第二VCO输出信号，以及第一和第二前馈分配器电路以分开第一和第二频率的第一和第二VCO输出信号通过第一和第二分频因子。该芯片还包括用于选择第一和第二分频因子的锁相环控制电路。描述和要求保护其他实施例。

73. 发明申请

US20080136531A1 Adaptive bandwidth phase locked loop with feedforward divider 有权
标题翻译：带前馈分频器的自适应带宽锁相环
公开(公告)号：US20080136531A1
公开(公告)日：2008-06-12
申请号：US11637254
申请日：2006-12-11
申请人： Jaeha Kim , Deog-Kyoon Jeong
发明人： Jaeha Kim , Deog-Kyoon Jeong
IPC分类号： H03L7/07
CPC分类号： H03L7/23 , H03L7/0895 , H03L7/093 , H03L7/0995
摘要： In some embodiments, a chip includes first and second sub phase lock loops (sub-PLLs) including first and second voltage controlled oscillators (VCOs) to provide first and second VCO output signals and first and second feedforward divider circuits to divide first and second frequencies of the first and second VCO output signals by first and second division factors. The chip also includes phase locked loop control circuitry to select the first and second division factors. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括第一和第二子锁相环（sub-PLL），其包括第一和第二压控振荡器（VCO），以提供第一和第二VCO输出信号，以及第一和第二前馈分配器电路以分开第一和第二频率的第一和第二VCO输出信号通过第一和第二分频因子。该芯片还包括用于选择第一和第二分频因子的锁相环控制电路。描述和要求保护其他实施例。

74. 发明申请

US20080126824A1 COMMUNICATIONS ARCHITECTURE FOR MEMORY-BASED DEVICES 有权
标题翻译：基于存储器件的通信架构
公开(公告)号：US20080126824A1
公开(公告)日：2008-05-29
申请号：US11828286
申请日：2007-07-25
申请人： Dongyun Lee , Yeshik Shin , David D. Lee , Deog-Kyoon Jeong , Shing Kong
发明人： Dongyun Lee , Yeshik Shin , David D. Lee , Deog-Kyoon Jeong , Shing Kong
IPC分类号： G06F1/08 , G06F12/02
CPC分类号： H04L47/10 , H04L47/245 , H04L47/34 , H04L47/365
摘要： A serial communications architecture for communicating between hosts and data store devices. The Storage Link architecture is specially adapted to support communications between multiple hosts and storage devices via a switching network, such as a storage area network. The Storage Link architecture specifies various communications techniques that can be combined to reduce the overall cost and increase the overall performance of communications. The Storage Link architecture may provide packet ordering based on packet type, dynamic segmentation of packets, asymmetric packet ordering, packet nesting, variable-sized packet headers, and use of out-of-band symbols to transmit control information as described below in more detail. The Storage Link architecture may also specify encoding techniques to optimize transitions and to ensure DC-balance.
摘要翻译：用于在主机和数据存储设备之间通信的串行通信架构。 Storage Link架构特别适用于通过交换网络（如存储区域网络）支持多个主机和存储设备之间的通信。存储链路架构规定了可以组合的各种通信技术，以降低总体成本并提高通信的整体性能。存储链路架构可以基于分组类型，分组的动态分段，不对称分组排序，分组嵌套，可变大小的分组报头以及使用带外符号来发送控制信息来提供分组排序，如以下更详细地描述的。存储链路架构还可以指定编码技术来优化转换并确保直流平衡。

75. 发明授权

US07203260B2 Tracked 3X oversampling receiver 有权
标题翻译：追踪3X过采样接收器
公开(公告)号：US07203260B2
公开(公告)日：2007-04-10
申请号：US10612840
申请日：2003-07-03
申请人： Yongsam Moon , Gijung Ahn , Deog-Kyoon Jeong
发明人： Yongsam Moon , Gijung Ahn , Deog-Kyoon Jeong
IPC分类号： H04L7/00 , H03L7/095 , H03D3/24
CPC分类号： H04L7/033 , H03L7/091 , H03L7/113 , H03L7/14 , H04L7/04 , Y10S331/02
摘要： A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.
摘要翻译：根据本发明实施例的接收数据的方法包括产生数据采样时钟信号并将接收的时钟信号与数据采样时钟信号进行比较的动作。数据采样时钟信号用于将数据信号采样成表示数据信号的第一区，第二区和第三区的采样数据。如果第一区域或第三区域具有转变，则确定采样数据的哪个区域具有数据信号的转变并且指示数据采样时钟信号的改变方向。

76. 发明授权

US07035351B1 Automatic gain control loop apparatus 有权
标题翻译：自动增益控制回路装置
公开(公告)号：US07035351B1
公开(公告)日：2006-04-25
申请号：US09705696
申请日：2000-11-06
申请人： Joonbae Park , Wonchan Kim , Kyeongho Lee , Deog-Kyoon Jeong
发明人： Joonbae Park , Wonchan Kim , Kyeongho Lee , Deog-Kyoon Jeong
IPC分类号： H03D3/18
CPC分类号： H04B1/30 , H03F3/211 , H03F2200/294 , H03F2200/372
摘要： A DC offset cancelling circuit with multiple feedback loops suppresses DC offset voltages within an automatic gain control loop apparatus. The apparatus includes a plurality of gain stages connected in series that receive and amplify an input RF signal. Each gain stage includes a corresponding feedback loop to filter the DC offset voltage accumulated in the respective gain stage.
摘要翻译：具有多个反馈环路的DC偏移消除电路抑制自动增益控制环路装置内的DC偏移电压。该装置包括串联连接的多个增益级，其接收和放大输入RF信号。每个增益级包括相应的反馈回路以对累积在相应增益级中的DC偏移电压进行滤波。

77. 发明授权

US06876240B2 Wide range multi-phase delay-locked loop 有权
标题翻译：宽范围多相延时锁定环路
公开(公告)号：US06876240B2
公开(公告)日：2005-04-05
申请号：US10722842
申请日：2003-11-25
申请人： Yongsam Moon , Gijung Ahn , Deog-Kyoon Jeong
发明人： Yongsam Moon , Gijung Ahn , Deog-Kyoon Jeong
IPC分类号： H03L7/091 , H03L7/113 , H03L7/14 , H04L7/033 , H04L7/04 , H03L7/06
CPC分类号： H04L7/033 , H03L7/091 , H03L7/113 , H03L7/14 , H04L7/04 , Y10S331/02
摘要： A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.
摘要翻译：延迟锁定环路装置包括：第一延迟元件，用于接收参考信号，延迟参考信号延迟时间，并输出第一延迟信号。第二延迟元件用于接收第一延迟信号，以将第一信号延迟信号延迟延迟时间，并输出第二延迟信号。还包括接收参考信号，第一延迟信号和第二延迟信号的谐波锁定防止电路，并且调整延迟时间，使得每个延迟信号的周期在预定范围内。

78. 发明授权

US06717468B1 Dynamically biased full-swing operation amplifier for an active matrix liquid crystal display driver 有权
标题翻译：用于有源矩阵液晶显示驱动器的动态偏置全摆幅运算放大器
公开(公告)号：US06717468B1
公开(公告)日：2004-04-06
申请号：US10215936
申请日：2002-08-08
申请人： Deog-Kyoon Jeong , Weon Jun Choe
发明人： Deog-Kyoon Jeong , Weon Jun Choe
IPC分类号： H03F345
CPC分类号： H03F3/3028 , H03F3/4521
摘要： A versatile amplifier circuit for driving a TFT LCD panel is disclosed. The amplifier circuit of the present comprises consists of a complementary input stage, biasing switches, and a rail-to-rail output stage. A signal-transfer switch determines which of two differential amplifiers in the input stage will drive the output stage of the amplifier. A biasing signal precharges a capacitor between the gates of output stage. The rail-to-rail output stage utilizes the precharged capacitor to maintain a voltage required to operate the output stage properly. A polarity signal is used to control the signal-transfer switch. The polarity signal specifies if a lower half of the input stage or an upper half of the input stage is used to drive the output stage of the amplifier circuit. A non-active transistor is kept turned-on above the threshold voltage for quick switching of the output driver. In one embodiment, a coupling capacitor is used between output stage transistors is for this purpose. This capacitor maintains the voltage necessary to keep the non-active transistor turned-on and flowing with a minimum current, and prevents the non-active transistor from being turned off. This simple scheme allows the amplifier circuit of the present invention to operate rapidly and in rail-to-rail range.
摘要翻译：公开了一种用于驱动TFT LCD面板的通用放大器电路。本发明的放大器电路包括互补输入级，偏置开关和轨到轨输出级。信号转换开关确定输入级中的两个差分放大器中的哪一个将驱动放大器的输出级。偏置信号在输出级的栅极之间对电容器进行预充电。轨到轨输出级利用预充电电容器来保持正确操作输出级所需的电压。极性信号用于控制信号转换开关。极性信号指定输入级的下半部分或输入级的上半部分是否用于驱动放大器电路的输出级。非活性晶体管保持接通高于阈值电压，以快速切换输出驱动器。在一个实施例中，在输出级晶体管之间使用耦合电容器用于此目的。该电容器保持使非活性晶体管导通并以最小电流流动所必需的电压，并且防止非有效晶体管截止。这种简单的方案允许本发明的放大器电路快速地并且在轨到轨范围内操作。

79. 发明授权

US06374361B1 Skew-insensitive low voltage differential receiver 有权
标题翻译：偏置低压差分接收器
公开(公告)号：US06374361B1
公开(公告)日：2002-04-16
申请号：US09298369
申请日：1999-04-22
申请人： Kyeongho Lee , Deog-Kyoon Jeong
发明人： Kyeongho Lee , Deog-Kyoon Jeong
IPC分类号： G06F104
CPC分类号： H03L7/0812 , G06F5/06 , H03L7/07 , H03L7/095 , H04L7/0337 , H04L25/14
摘要： An apparatus for correcting skew between data signals and a clock signal in a system where the data and clock signals are transmitted and using low-voltage differential swing is disclosed. The apparatus comprises, in one embodiment, a delay locked loop, for converting the LVDS clock signal into a full-swing clock signal and generating a plurality of clock recovery signals from the converted full-swing clock signal, and a plurality of data recovery signals from the converted full-swing clock signal, and a plurality of data recovery channels, each channel coupled to a data signal and comprising an LVDS converter, a skew adjust circuit, a sampler array, a phase adjusting circuit. The delay locked loop and the data channel circuitry combine to remove skew from LVDS signals by generating multiple clock signals, sampling the data at multiple intervals, using the samples to eliminate skew, and retrieving correct data samples from the data signals. In another embodiment, the sampler array comprises a plurality of transition sampling circuits, for sampling transitions between two adjacent serial bits of data and generating a lock signal and a sampled data signal responsive to the sampled transition, and a plurality of center sampling circuits, for sampling a center position of each serial bit of data and generating a center sample signal responsive to the sample, and the phase adjusting circuit generating skew control signals responsive to the center sample signals, lock signals, and transition data signals received from the sampler array.
摘要翻译：公开了一种用于校正数据信号与发送数据和时钟信号并使用低电压差动摆幅的系统中的时钟信号之间的偏差的装置。该装置在一个实施例中包括延迟锁定环路，用于将LVDS时钟信号转换成全频时钟信号并从转换的全摆频时钟信号产生多个时钟恢复信号，以及多个数据恢复信号来自转换的全摆频时钟信号和多个数据恢复通道，每个通道耦合到数据信号并且包括LVDS转换器，偏斜调整电路，采样器阵列，相位调整电路。延迟锁定环路和数据通道电路结合起来，通过产生多个时钟信号，通过使用采样来消除偏差并从数据信号中检索出正确的数据样本，以多个时间间隔对数据进行采样，消除了LVDS信号的偏移。在另一个实施例中，采样器阵列包括多个转换采样电路，用于在两个相邻串行数据位之间进行采样转换，并产生响应采样转换的锁定信号和采样数据信号，以及多个中心采样电路，用于采样数据的每个串行位的中心位置，并响应于采样产生一个中心采样信号，相位调整电路根据从采样器阵列接收的中心采样信号，锁定信号和转换数据信号产生偏斜控制信号。

80. 发明授权

US6144242A Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequencies 有权
标题翻译：多个同步信号中的可控延迟，用于降低峰值频率时的电磁干扰
公开(公告)号：US6144242A
公开(公告)日：2000-11-07
申请号：US148815
申请日：1998-09-04
申请人： Deog-Kyoon Jeong , Gyudong Kim , David D. Lee
发明人： Deog-Kyoon Jeong , Gyudong Kim , David D. Lee
IPC分类号： H04B3/04 , H04L25/08 , H03H11/26
CPC分类号： H04L25/085
摘要： Multiple controllable delays reduce EMI radiated during the transmission of multiple synchronized signals. Each controllable delay introduces a controlled delay into a corresponding signal being transmitted. The controlled delay is such that the combined strength of the multiple signals at peak frequencies is substantially reduced. This results in reduced EMI radiation at those peak frequencies.
摘要翻译：多个可控延迟降低了传输多个同步信号期间的EMI辐射。每个可控延迟将受控的延迟引入正在传输的相应信号。受控的延迟使得峰值频率处的多个信号的组合强度显着降低。这导致在那些峰值频率下降低了EMI辐射。

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