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71. 发明授权

US5940340A Method and apparatus for writing to memory components 失效
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：US5940340A
公开(公告)日：1999-08-17
申请号：US858068
申请日：1997-05-16
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：提供额外的操作模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

72. 发明授权

US5844855A Method and apparatus for writing to memory components 失效
公开(公告)号：US5844855A
公开(公告)日：1998-12-01
申请号：US858014
申请日：1997-05-16
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

73. 发明授权

US07003639B2 Memory controller with power management logic 失效
公开(公告)号：US07003639B2
公开(公告)日：2006-02-21
申请号：US10873670
申请日：2004-06-21
申请人： Ely K. Tsern , Ramprasad Satagopan , Richard M. Barth , Steven C. Woo
发明人： Ely K. Tsern , Ramprasad Satagopan , Richard M. Barth , Steven C. Woo
IPC分类号： G06F12/00
CPC分类号： G06F1/3275 , G06F1/3203 , G06F12/0215 , G06F2212/1028 , G11C11/4074 , Y02D10/13 , Y02D10/14
摘要： A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

74. 发明授权

US06754783B2 Memory controller with power management logic 有权
公开(公告)号：US06754783B2
公开(公告)日：2004-06-22
申请号：US10369301
申请日：2003-02-18
申请人： Ely K. Tsern , Ramprasad Satagopan , Richard M. Barth , Steven C. Woo
发明人： Ely K. Tsern , Ramprasad Satagopan , Richard M. Barth , Steven C. Woo
IPC分类号： G06F1200
CPC分类号： G06F1/3275 , G06F1/3203 , G06F12/0215 , G06F2212/1028 , G11C11/4074 , Y02D10/13 , Y02D10/14
摘要： A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

75. 发明授权

US06523089B2 Memory controller with power management logic 有权
公开(公告)号：US06523089B2
公开(公告)日：2003-02-18
申请号：US09907338
申请日：2001-07-16
申请人： Ely K. Tsern , Ramprasad Satagopan , Richard M. Barth , Steven C. Woo
发明人： Ely K. Tsern , Ramprasad Satagopan , Richard M. Barth , Steven C. Woo
IPC分类号： G06F1200
CPC分类号： G06F1/3275 , G06F1/3203 , G06F12/0215 , G06F2212/1028 , G11C11/4074 , Y02D10/13 , Y02D10/14
摘要： A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal. Command issue circuitry issues power state commands and access commands to the dynamic memory devices in accordance with the at least one command selection signal and the address in the memory access request.

76. 发明授权

US07565468B2 Integrated circuit memory device and signaling method for adjusting drive strength based on topography of integrated circuit devices 有权
标题翻译：集成电路存储器件和基于集成电路器件形貌调整驱动强度的信令方法
公开(公告)号：US07565468B2
公开(公告)日：2009-07-21
申请号：US11929974
申请日：2007-10-30
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00 , G05F1/10
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device includes an output driver, a first register to store a value representative of a drive strength setting of the output driver, wherein the value is determined based on information stored in a supplemental memory device external to the integrated circuit memory device, and a transmitter circuit configurable to receive the value representative of a drive strength setting of the output driver. The output driver is configurable to output data synchronously with respect to an external clock signal.
摘要翻译：集成电路装置包括输出驱动器，第一寄存器，用于存储代表输出驱动器的驱动强度设置的值，其中该值基于存储在集成电路存储器件外部的补充存储器件中的信息确定，以及发射机电路可配置为接收代表输出驱动器的驱动强度设置的值。输出驱动器可配置为相对于外部时钟信号同步输出数据。

77. 发明授权

US07174400B2 Integrated circuit device that stores a value representative of an equalization co-efficient setting 有权
标题翻译：集成电路装置，其存储代表均衡系数设定的值
公开(公告)号：US07174400B2
公开(公告)日：2007-02-06
申请号：US11181411
申请日：2005-07-13
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit device is described. The integrated circuit device includes a transmitter circuit having an output driver to output data, and a register to store a value representative of an equalization co-efficient setting of the output driver. The value may be determined based on information stored in a supplemental memory device.
摘要翻译：描述集成电路器件。集成电路装置包括具有用于输出数据的输出驱动器的发送器电路和用于存储表示输出驱动器的均衡均衡设置的值的寄存器。该值可以基于存储在补充存储器件中的信息来确定。

78. 发明授权

US07051129B2 Memory device having programmable drive strength setting 有权
标题翻译：具有可编程驱动强度设置的存储器
公开(公告)号：US07051129B2
公开(公告)日：2006-05-23
申请号：US10881433
申请日：2004-06-29
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topography dependent parameter for later use by the parameter adjustment circuitry. The parameter adjustment circuitry adjusts a parameter control signal in accordance with the topography dependent parameter, which is coupled to the output driver. Prior to driving an output signal onto a bus, the output driver adjusts the transmit signal characteristic in accordance with the parameter control signal. Similarly, in a bus receiver, a receive signal characteristic is adjusted in response to a topography dependent parameter.
摘要翻译：通过根据一个或多个地形相关参数调整信号特性来优化总线通信。在总线发送器中，根据地形相关参数来调整发送信号特性。总线发射器中的端口接收地形相关参数，供以后由参数调整电路使用。参数调整电路根据与输出驱动器耦合的地形相关参数来调整参数控制信号。在将输出信号驱动到总线之前，输出驱动器根据参数控制信号调整发送信号特性。类似地，在总线接收器中，响应于地形相关参数来调整接收信号特性。

79. 发明申请

US20090248971A1 System and Dynamic Random Access Memory Device Having a Receiver 有权
标题翻译：具有接收器的系统和动态随机存取存储器件
公开(公告)号：US20090248971A1
公开(公告)日：2009-10-01
申请号：US12479679
申请日：2009-06-05
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F12/06 , G06F13/28 , G06F3/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： A dynamic random access memory device (DRAM) receiver circuit includes an input to receive a data signal, and also includes decision circuitry to make a decision about the received data signal based on a present sampled data signal and a coefficient value corresponding to at least one of a previously sampled data signals.
摘要翻译：动态随机存取存储器件（DRAM）接收器电路包括用于接收数据信号的输入端，并且还包括判定电路，用于基于当前采样的数据信号和对应于至少一个的先前采样的数据信号。

80. 发明授权

US07032057B2 Integrated circuit with transmit phase adjustment 有权
标题翻译：具有发射相位调整的集成电路
公开(公告)号：US07032057B2
公开(公告)日：2006-04-18
申请号：US10742247
申请日：2003-12-19
申请人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
发明人： Mark A. Horowitz , Richard M. Barth , Craig E. Hampel , Alfredo Moncayo , Kevin S. Donnelly , Jared L. Zerbe
IPC分类号： G06F13/00
CPC分类号： G06F13/4291 , G06F3/061 , G06F3/0611 , G06F3/0619 , G06F3/0658 , G06F3/0661 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F12/1081 , G06F13/102 , G06F13/1689 , G06F13/364 , G06F13/4072 , G06F13/4086 , G06F13/4234 , G06F13/4243 , G06F2206/1014 , G06F2212/7201 , G11C5/04 , G11C5/063 , G11C7/1048 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C16/32 , G11C19/00 , H03K19/00384 , H03K19/018585
摘要： An integrated circuit that communicates with a plurality of other integrated circuit devices includes a transmitter circuit to transmit data to an external signal line and a first register to store a first value representative of a transmit phase adjustment that is used to adjust when the transmit data is transmitted. The first value is determined based on information specifying a configuration of the plurality of other integrated circuit devices.
摘要翻译：与多个其他集成电路装置进行通信的集成电路包括：发送器电路，用于向外部信号线发送数据;以及第一寄存器，用于存储表示发送相位调整的第一值，所述第一值用于在发送数据为传输。基于指定多个其他集成电路装置的配置的信息来确定第一值。

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