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71. 发明授权

US06459482B1 Grainless material for calibration sample 失效
标题翻译：用于校准样品的粗糙材料
公开(公告)号：US06459482B1
公开(公告)日：2002-10-01
申请号：US09729294
申请日：2000-12-04
申请人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Michael K. Templeton , Sanjay K. Yedur , Bryan K. Choo
发明人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Michael K. Templeton , Sanjay K. Yedur , Bryan K. Choo
IPC分类号： G01J110
CPC分类号： H01J37/28 , H01J2237/2826
摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.
摘要翻译：本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。校准标准品具有非晶体材料如非晶硅形成的特征。无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

72. 发明授权

US06451621B1 Using scatterometry to measure resist thickness and control implant 有权
标题翻译：使用散射法测量抗蚀剂厚度和控制植入
公开(公告)号：US06451621B1
公开(公告)日：2002-09-17
申请号：US10050732
申请日：2002-01-16
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L2166
CPC分类号： H01L22/12
摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.
摘要翻译：本发明提供了系统和方法，其中使用散射法来控制植入过程，例如成角度的植入过程。根据本发明，与抗蚀剂尺寸相关的数据通过在植入工艺之前的散射测量获得。该数据用于确定抗蚀剂是否适合于植入过程，和/或确定用于植入过程的适当条件，例如植入角度或植入剂量。

73. 发明授权

US06445072B1 Deliberate void in innerlayer dielectric gapfill to reduce dielectric constant 有权
标题翻译：内层介质间隙填料中的有意的空隙以降低介电常数
公开(公告)号：US06445072B1
公开(公告)日：2002-09-03
申请号：US09617158
申请日：2000-07-17
申请人： Ramkumar Subramanian , Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan
发明人： Ramkumar Subramanian , Bhanwar Singh , Michael K. Templeton , Bharath Rangarajan
IPC分类号： H01L214763
CPC分类号： H01L21/7682 , Y10S977/897
摘要： One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.
摘要翻译：本发明的一个方面涉及一种形成内层电介质的方法，包括以下步骤：提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层，所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。本发明的另一方面涉及一种内层电介质半导体结构，其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层，保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层，所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。

74. 发明授权

US06413857B1 Method of creating ground to avoid charging in SOI products 有权
标题翻译：创建地面以避免在SOI产品中充电的方法
公开(公告)号：US06413857B1
公开(公告)日：2002-07-02
申请号：US09824349
申请日：2001-04-02
申请人： Ramkumar Subramanian , Bharath Rangarajan , Bhanwar Singh
发明人： Ramkumar Subramanian , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L214763
CPC分类号： H01L29/66772 , H01L21/743 , H01L21/84 , H01L29/78612 , H01L29/78645 , H01L29/78648
摘要： An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A plurality of local interconnects are formed from a top insulating layer to a top silicon layer of the SOI device structure. A ground contact is then formed from the top insulating layer to a bottom substrate layer of the SOI device structure. The ground contact extends through the insulating layer, an isolation region and an oxide layer to the bottom substrate layer.
摘要翻译：提供了SOI器件结构，其有助于减轻由浮体效应引起的电荷积累。多个局部互连由SOI器件结构的顶部绝缘层到顶部硅层形成。然后从顶部绝缘层到SOI器件结构的底部基底层形成接地触点。接地触头延伸穿过绝缘层，隔离区域和氧化物层延伸到底部基底层。

75. 发明授权

US06354133B1 Use of carbon nanotubes to calibrate conventional tips used in AFM 失效
标题翻译：使用碳纳米管校准AFM中使用的常规提示
公开(公告)号：US06354133B1
公开(公告)日：2002-03-12
申请号：US09729293
申请日：2000-12-04
申请人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
发明人： Sanjay K. Yedur , Bhanwar Singh , Bryan K. Choo , Michael K. Templeton , Ramkumar Subramanian
IPC分类号： G01B528
CPC分类号： G01Q40/02 , G01Q40/00 , Y10S977/742 , Y10S977/842 , Y10S977/849 , Y10S977/85 , Y10S977/876 , Y10S977/901
摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.
摘要翻译：本发明提供了用于校准纳米测量装置的系统，方法和标准。本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。碳纳米管校准标准品的宽度以高精度已知。考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

76. 发明授权

US06262484B1 Dual damascene method for backened metallization using poly stop layers 有权
公开(公告)号：US06262484B1
公开(公告)日：2001-07-17
申请号：US09295812
申请日：1999-04-20
申请人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
发明人： Bharath Rangarajan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： H01L23485
CPC分类号： H01L21/76807
摘要： A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.

77. 发明授权

US06190062B1 Cleaning chamber built into SEM for plasma or gaseous phase cleaning 有权
标题翻译：内置扫描电镜的清洗室进行等离子体或气相清洗
公开(公告)号：US06190062B1
公开(公告)日：2001-02-20
申请号：US09558492
申请日：2000-04-26
申请人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Bryan K. Choo , Sanjay K. Yedur
发明人： Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh , Bryan K. Choo , Sanjay K. Yedur
IPC分类号： G03D1300
CPC分类号： H01J37/28 , H01J2237/2817
摘要： One aspect of the present invention relates to a method of inspecting a patterned substrate using an SEM, involving the steps of evaluating the patterned substrate to determine if charges exist thereon; introducing the patterned substrate having charges thereon into a processing chamber of the SEM; inspecting the patterned resist using an electron beam generated by the SEM; and introducing a cleaner containing ozone into the processing chamber of the SEM. Another aspect of the present invention relates to a system for processing a patterned substrate, containing a charge sensor for determining if charges exist on the patterned substrate and measuring the charges; a means for contacting the patterned substrate with a cleaner containing ozone to reduce the charges thereon; a controller for setting at least one of time of contact between the patterned substrate and the cleaner, temperature of the cleaner, concentration of ozone in the cleaner, and pressure under which contact between the patterned substrate and the cleaner occurs; and a device for inspecting the patterned substrate with an electron beam.
摘要翻译：本发明的一个方面涉及使用SEM检查图案化衬底的方法，包括以下步骤：评估图案化衬底以确定其中是否存在电荷; 将具有电荷的图案化衬底引入到SEM的处理室中; 使用由SEM产生的电子束检查图案化的抗蚀剂; 并将含有臭氧的清洁剂引入SEM的处理室。本发明的另一方面涉及一种用于处理图案化衬底的系统，其包含用于确定在图案化衬底上是否存在电荷并测量电荷的电荷传感器; 用于使图案化基底与含有臭氧的清洁剂接触以降低其上的电荷的装置; 用于设置图案化基板和清洁器之间的接触时间中的至少一个的控制器，清洁器的温度，清洁器中的臭氧浓度以及图案化基板和清洁器之间的接触发生的压力; 以及用于用电子束检查图案化衬底的装置。

78. 发明授权

US07799514B1 Surface treatment with an acidic composition to prevent substrate and environmental contamination 有权
标题翻译：用酸性组合物进行表面处理，以防止底物和环境污染
公开(公告)号：US07799514B1
公开(公告)日：2010-09-21
申请号：US10957367
申请日：2004-10-01
申请人： Ramkumar Subramanian , Bhanwar Singh , Gilles Amblard
发明人： Ramkumar Subramanian , Bhanwar Singh , Gilles Amblard
IPC分类号： G03F7/26
CPC分类号： G03F7/265
摘要： Disclosed are methods for eliminating and/or mitigating the formation of footing and/or T-tops in a resist pattern. A substrate with or without an antireflective coating layer may be treated with an acidic composition prior to the formation of a resist layer. The acid treatment prevents the loss of photo generated acid from the resist by either quenching and/or neutralizing the bases, and thereby reduces the formation of footing. The surface of a resist layer which has been irradiated may be treated with an acidic composition prior to post-exposure bake. The acid treatment prevents the loss of photo generated acid from the resist by either compensating for the evaporation and/or neutralization of the bases and thereby prevents the formation of T-tops.
摘要翻译：公开了用于消除和/或减轻抗蚀剂图案中的基脚和/或T形顶部的形成的方法。具有或不具有抗反射涂层的基底可以在形成抗蚀剂层之前用酸性组合物处理。酸处理通过淬灭和/或中和碱来防止光阻产生的酸的损失，从而减少基底的形成。已经照射的抗蚀剂层的表面可以在曝光前烘烤之前用酸性组合物处理。酸处理通过补偿基底的蒸发和/或中和来防止光致抗蚀剂产生的光的损失，从而防止形成T形顶部。

79. 发明授权

US07224456B1 In-situ defect monitor and control system for immersion medium in immersion lithography 有权
标题翻译：浸没式光刻浸渍介质的原位缺陷监测和控制系统
公开(公告)号：US07224456B1
公开(公告)日：2007-05-29
申请号：US10858759
申请日：2004-06-02
申请人： Khoi Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
发明人： Khoi Phan , Bhanwar Singh , Bharath Rangarajan , Ramkumar Subramanian
IPC分类号： G01N15/02
CPC分类号： G01N21/47 , G01N2015/0011 , G03F7/70341
摘要： A system and method for detecting bubbles in a lithographic immersion medium and for controlling a lithographic process based at least in part on the detection of bubbles is provided. A bubble monitoring component emits an incident beam that passes through the immersion medium and is incident upon a substrate to produce a reflected and/or diffracted beam(s). The reflected and/or diffracted beam(s) is received by one or more optical detectors. The presence or absence of bubbles can be derived from information extracted by scatterometry from the reflected and/or diffracted beams. A process control component interacts with a positioning component and an optical exposure component to alter a lithographic process based at least in part on the results of the scatterometry.
摘要翻译：提供了一种用于在光刻浸渍介质中检测气泡并且至少部分地基于气泡检测来控制光刻工艺的系统和方法。气泡监测部件发射穿过浸没介质并入射到基板上以产生反射和/或衍射光束的入射光束。反射和/或衍射光束被一个或多个光学检测器接收。可以通过从反射和/或衍射光束散射法提取的信息导出气泡的存在或不存在。过程控制部件与定位部件和光学曝光部件相互作用，以至少部分地基于散射测量的结果来改变光刻工艺。

80. 发明授权

US07187796B1 Systems and methods that employ exposure compensation to provide uniform CD control on reticle during fabrication 失效
标题翻译：使用曝光补偿的系统和方法在制造过程中对掩模版提供均匀的CD控制
公开(公告)号：US07187796B1
公开(公告)日：2007-03-06
申请号：US10676613
申请日：2003-10-01
申请人： Khoi A. Phan , Ramkumar Subramanian , Bhanwar Singh
发明人： Khoi A. Phan , Ramkumar Subramanian , Bhanwar Singh
IPC分类号： G06K9/00
CPC分类号： B82Y40/00 , B82Y10/00 , G03F1/78 , H01J37/3174
摘要： The present invention relates to monitoring and controlling a reticle fabrication process (e.g. employed with an electron beam lithography process). A typical fabrication process involves discrete stages including exposure, post-exposure bake and development. After fabrication is complete, an inspection can be performed on the reticle to determine whether any parameters during fabrication and/or any data points are outside of acceptable tolerances. The data is collected and fed into an algorithm (e.g. data-mining algorithm) utilized to determine which fabrication parameters need to be modified then sends the data to a control system (e.g. advanced process control) to facilitate needed changes to the fabrication parameters.
摘要翻译：本发明涉及监测和控制掩模版制造工艺（例如采用电子束光刻工艺）。典型的制造过程涉及离散阶段，包括曝光，曝光后烘烤和显影。制造完成后，可以对掩模版进行检查，以确定制造期间和/或任何数据点中的任何参数是否超出可接受的公差。收集数据并将其馈送到用于确定哪些制造参数需要被修改的算法（例如数据挖掘算法）中，然后将数据发送到控制系统（例如高级过程控制），以便于对制造参数的所需改变。

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