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71. 发明授权

US06980014B2 Interposer and methods for fabricating same 失效
标题翻译：插件及其制造方法
公开(公告)号：US06980014B2
公开(公告)日：2005-12-27
申请号：US10379221
申请日：2003-03-04
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： G01R1/04 , H05K1/11 , H05K1/14 , H05K3/34 , G01R31/02
CPC分类号： H05K7/1061 , B33Y10/00 , B33Y30/00 , B33Y80/00 , G01R1/0408 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/07378 , G01R3/00 , H01L23/32 , H01L23/49827 , H01L2224/16111 , H01L2224/16237 , H01L2224/8114 , H01L2224/81385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01049 , H01L2924/01082 , H01L2924/12042 , H01L2924/12044 , H01L2924/15787 , H01L2924/351 , H05K1/112 , H05K1/141 , H05K3/3436 , H05K2201/049 , H05K2201/09472 , H05K2201/10378 , H05K2201/10734 , H05K2201/2018 , H05K2203/167 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49147 , Y10T29/49156 , Y10T29/49165 , Y10T29/49204 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： An interposer including a fence that receives and aligns a semiconductor device, such as a flip-chip type semiconductor device, with a substrate. The fence may include edges that are configured to progressively align a semiconductor device with the substrate. The fence may also include one or more laterally recessed regions to facilitate rough alignment of a semiconductor device with the substrate. Methods for fabricating the fence include the use of stereolithographic and molding processes. When stereolithography is used to fabricate the fence, a machine vision system that includes at least one camera operably associated with a computer may be used to control a stereolithography apparatus and facilitates recognition of the position and orientation of substrates on and around which material is to be applied in one or more layers to form the fence. As a result, the substrates need not be precisely mechanically aligned.
摘要翻译：一种插入器，包括接收半导体器件（例如倒装芯片型半导体器件）和衬底的栅栏。栅栏可以包括被配置为逐渐地将半导体器件与衬底对准的边缘。栅栏还可以包括一个或多个侧向凹入的区域，以便于半导体器件与衬底的粗略对准。围栏的制造方法包括使用立体光刻和成型工艺。当使用立体光刻制造栅栏时，可以使用包括与计算机可操作地相关联的至少一个照相机的机器视觉系统来控制立体光刻设备，并且有助于识别材料在其上和周围的位置和取向施加在一个或多个层中以形成栅栏。因此，基板不需要精确地机械对准。

72. 发明授权

US06670634B2 Silicon carbide interconnect for semiconductor components 失效
标题翻译：用于半导体元件的碳化硅互连
公开(公告)号：US06670634B2
公开(公告)日：2003-12-30
申请号：US10351742
申请日：2003-01-27
申请人： Salman Akram , Alan G. Wood
发明人： Salman Akram , Alan G. Wood
IPC分类号： H01L2358
CPC分类号： G01R1/06711 , G01R1/07314 , H01L23/13 , H01L23/498 , H01L23/49872 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.
摘要翻译：用于半导体部件的互连件包括衬底和衬底上的互连触点，用于电连接部件上的组件触点。互连触点包括碳化硅导电层和与碳化硅导电层电连通的导体。碳化硅导电层提供耐磨表面，并且改善部件触点和互连触点之间的热传递。碳化硅导电层可以包括掺杂的碳化硅，或交替地热氧化的碳化硅。互连可以被配置用于与用于测试分立元件（例如骰子或芯片尺寸封装）的测试设备一起使用，或者替代地与用于测试晶片尺寸的元件（例如晶片，面板和板）的测试设备一起使用。此外，互连可以被配置用于构造半导体封装和诸如多芯片模块的电子组件。

73. 发明授权

US06570251B1 Under bump metalization pad and solder bump connections 有权
标题翻译：欠凸极金属化焊盘和焊料凸块连接
公开(公告)号：US06570251B1
公开(公告)日：2003-05-27
申请号：US09388436
申请日：1999-09-02
申请人： Salman Akram , Alan G. Wood
发明人： Salman Akram , Alan G. Wood
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L24/03 , H01L24/11 , H01L24/12 , H01L2224/0231 , H01L2224/0401 , H01L2224/05559 , H01L2224/05624 , H01L2224/05647 , H01L2224/05664 , H01L2224/1134 , H01L2224/1148 , H01L2224/13023 , H01L2224/131 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/05042 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： The present invention relates to an improved method of forming and structure for under bump metallurgy (“UBM”) pads for a flip chip which reduces the number of metal layers and requires the use of only a single passivation layer to form, thus eliminating a masking step required in typical prior art processes. The method also includes repatterning bond pad locations.
摘要翻译：本发明涉及一种用于倒装芯片的凸块下金属（“UBM”）焊盘的形成和结构的改进方法，其减少金属层的数量，并且仅需要使用单个钝化层来形成，从而消除掩模在典型的现有技术方法中所需的步骤。该方法还包括重新形成接合焊盘位置。

74. 发明授权

US06548392B2 Methods of a high density flip chip memory arrays 有权
标题翻译：高密度倒装芯片存储阵列的方法
公开(公告)号：US06548392B2
公开(公告)日：2003-04-15
申请号：US09398337
申请日：1999-09-17
申请人： Salman Akram , Warren M. Farnworth , Alan G. Wood
发明人： Salman Akram , Warren M. Farnworth , Alan G. Wood
IPC分类号： H01L2144
CPC分类号： H01L24/81 , H01L23/552 , H01L23/556 , H01L27/10897 , H01L2224/05001 , H01L2224/05027 , H01L2224/05572 , H01L2224/13111 , H01L2224/1319 , H01L2224/16 , H01L2224/274 , H01L2224/81801 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H01L2924/00
摘要： A low alpha emissivity-induced error solder bump, flip-chip integrated circuit device. The device includes a semiconductor die having an active surface and a bond pad array disposed about the active surface of the die. The active surface of the die includes logic circuits adjacent memory cell arrays. Each of the bond pads directly overlays a logic circuit, to which they may be connected. The present invention also includes methods for designing and fabricating the invented devices and connecting them to a carrier substrate.
摘要翻译：低α辐射率引起的误差焊料凸块，倒装芯片集成电路器件。该器件包括具有活动表面的半导体管芯和围绕管芯的有效表面设置的接合焊盘阵列。芯片的有源表面包括与存储单元阵列相邻的逻辑电路。每个接合焊盘直接覆盖它们可以连接到的逻辑电路。本发明还包括用于设计和制造本发明的装置并将其连接到载体基板的方法。

75. 发明授权

US06287942B1 Hermetic chip and method of manufacture 有权
标题翻译：密封芯片和制造方法
公开(公告)号：US06287942B1
公开(公告)日：2001-09-11
申请号：US09518293
申请日：2000-03-03
申请人： Warren M. Farnworth , Salman Akram , Alan G. Wood
发明人： Warren M. Farnworth , Salman Akram , Alan G. Wood
IPC分类号： H01L21301
CPC分类号： H01L24/05 , H01L21/56 , H01L23/291 , H01L23/3107 , H01L24/03 , H01L24/48 , H01L2224/04042 , H01L2224/05556 , H01L2224/05599 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48464 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01022 , H01L2924/01031 , H01L2924/01032 , H01L2924/01074 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10253 , Y10S438/958 , Y10S438/959 , H01L2224/45099 , H01L2924/00 , H01L2224/85399
摘要： A fully hermetically sealed semiconductor chip and its method of manufacture. The semiconductor chip of the present invention is fully hermetically sealed on both sides and the edges thereof through the use of suitable coatings applied thereto, such as glass, to prevent an environmental attack of the semiconductor chip. The fully hermetically sealed semiconductor chip of the present invention does not require the use of a separate package for the hermetic sealing of the chip, thereby reducing the size of such a chip. The method of the manufacture of the semiconductor chip of the present invention provides a simple process the fully hermetic sealing of both sides and the edges of the semiconductor chip out the use of a separate package.
摘要翻译：一种完全密封的半导体芯片及其制造方法。本发明的半导体芯片通过使用适用于其上的合适的涂层（例如玻璃）在其两侧及其边缘上完全气密密封，以防止半导体芯片的环境攻击。本发明的完全密封的半导体芯片不需要使用用于芯片的气密密封的单独封装，从而减小这种芯片的尺寸。本发明的半导体芯片的制造方法提供了使用单独的封装完全密封半导体芯片的两侧和边缘的简单工艺。

76. 发明授权

US06228687B1 Wafer-level package and methods of fabricating 有权
标题翻译：晶圆级封装及其制造方法
公开(公告)号：US06228687B1
公开(公告)日：2001-05-08
申请号：US09340513
申请日：1999-06-28
申请人： Salman Akram , Alan G. Wood
发明人： Salman Akram , Alan G. Wood
IPC分类号： H01L2144
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/06 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/13099 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01075 , H01L2924/01079 , H01L2924/014 , H01L2924/12042 , H01L2924/12044 , H01L2924/00
摘要： A carrier for use in a chip-scale package, including a polymeric film with apertures defined therethrough. The apertures, which are alignable with corresponding bond pads of a semiconductor device, each include a quantity of conductive material extending substantially through the length thereof. The carrier may also include laterally extending conductive traces in contact with or otherwise in electrical communication with the conductive material in the apertures of the carrier. Contacts may be disposed on a backside surface of the carrier. The contacts may communicate with the conductive material disposed in the apertures of the carrier. A conductive bump, such as a solder bump, may be disposed adjacent each or any of the contacts. A chip-scale package including the carrier of the present invention is also within the scope of the present invention. Such a chip-scale package includes a semiconductor device invertedly disposed over the carrier such that bond pads of the semiconductor device substantially align with apertures formed through the carrier. Thus, the bond pads of the semiconductor device may communicate with the conductive bumps by means of the conductive material disposed in the apertures of the carrier. Methods of fabricating the carrier of the present invention and methods of fabricating chip-scale packages including the carrier are also within the scope of the present invention.
摘要翻译：用于芯片级封装的载体，包括具有通过其定义的孔的聚合物膜。与半导体器件的相应接合焊盘对准的孔各自包括大体上延伸通过其长度的一定数量的导电材料。载体还可以包括与载体的孔中的导电材料接触或以其他方式与电连通的横向延伸的导电迹线。触点可以设置在载体的背面上。触点可以与布置在载体的孔中的导电材料连通。诸如焊料凸块的导电凸块可以设置在每个或任何触点附近。包括本发明的载体的芯片级封装也在本发明的范围内。这种芯片级封装包括反向设置在载体上的半导体器件，使得半导体器件的接合焊盘基本上与通过载体形成的孔对准。因此，半导体器件的接合焊盘可以通过设置在载体的孔中的导电材料与导电凸块连通。制造本发明的载体的方法和包括载体的芯片级封装的制造方法也在本发明的范围内。

77. 发明授权

US6002180A Multi chip module with conductive adhesive layer 失效
标题翻译：多芯片模块带导电胶层
公开(公告)号：US6002180A
公开(公告)日：1999-12-14
申请号：US65361
申请日：1998-04-23
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H05K3/32 , H05K3/40 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/83 , H01L21/563 , H01L23/13 , H01L24/29 , H01L24/81 , H01L2224/1319 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/73203 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/30105 , H05K3/321 , H05K3/4007
摘要： A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.
摘要翻译：提供了一种用于形成诸如多芯片模块或存储器模块的芯片模块的方法。多芯片模块包括被配置为在其上安装多个半导体晶片的衬底。衬底包括形成为对应于骰子上的接合焊盘的位置的图案的凸起接触构件。在基板上的接触构件和骰子上的接合垫之间形成各向异性导电粘合剂层，以将骰子固定到基板上并在其间形成电连接。此外，可以在骰子和衬底之间形成底部填充层以填充它们之间的间隙，并进一步将骰子固定到衬底上。形成在基板上的导体和输入/输出焊盘形成到和接触构件的电路。为了形成存储器模块，可以将一个或多个多芯片模块安装到具有与导体电连通的边缘连接器和基板上的接触部件的支撑基板。

78. 发明授权

US5789278A Method for fabricating chip modules 失效
标题翻译：制造芯片模块的方法
公开(公告)号：US5789278A
公开(公告)日：1998-08-04
申请号：US688368
申请日：1996-07-30
申请人： Salman Akram , Alan G. Wood , Warren M. Farnworth
发明人： Salman Akram , Alan G. Wood , Warren M. Farnworth
IPC分类号： H01L21/56 , H01L21/60 , H01L23/13 , H05K3/32 , H05K3/40 , H01L21/44
CPC分类号： H01L24/83 , H01L21/563 , H01L23/13 , H01L24/29 , H01L24/81 , H01L2224/1319 , H01L2224/29101 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/73203 , H01L2224/81801 , H01L2224/8319 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/07811 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15151 , H01L2924/30105 , H05K3/321 , H05K3/4007
摘要： A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.
摘要翻译：提供了一种用于形成诸如多芯片模块或存储器模块的芯片模块的方法。多芯片模块包括被配置为在其上安装多个半导体晶片的衬底。衬底包括形成为对应于骰子上的接合焊盘的位置的图案的凸起接触构件。在基板上的接触构件和骰子上的接合垫之间形成各向异性导电粘合剂层，以将骰子固定到基板上并在其间形成电连接。此外，可以在骰子和衬底之间形成底部填充层以填充它们之间的间隙，并进一步将骰子固定到衬底上。形成在基板上的导体和输入/输出焊盘形成到和接触构件的电路。为了形成存储器模块，可以将一个或多个多芯片模块安装到具有与导体电连通的边缘连接器和基板上的接触部件的支撑基板。

79. 发明授权

US08324100B2 Methods of forming conductive vias 有权
标题翻译：形成导电通孔的方法
公开(公告)号：US08324100B2
公开(公告)日：2012-12-04
申请号：US13029950
申请日：2011-02-17
申请人： Salman Akram , William Mark Hiatt , Steven Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steven Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer.
摘要翻译：形成导电通孔的方法可以包括部分地穿过衬底形成盲孔，在衬底的表面上形成铝膜，从一些表面去除铝膜的第一部分，将导电材料选择性地沉积到第二部分上铝膜，并且通过基板的背面露出盲孔。制造导电通孔的方法可以包括通过至少一个未镀覆的焊盘形成至少一个通孔，在至少一个通孔的至少一个表面上形成第一粘合剂，在第一粘合剂上形成电介质，形成基底层叠在电介质和至少一个未镀覆的焊盘上，并将镍镀在基底层上。

80. 发明授权

US08294273B2 Methods for fabricating and filling conductive vias and conductive vias so formed 有权
标题翻译：制造和填充如此形成的导电通孔和导电通孔的方法
公开(公告)号：US08294273B2
公开(公告)日：2012-10-23
申请号：US12985570
申请日：2011-01-06
申请人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
发明人： Salman Akram , William Mark Hiatt , Steve Oliver , Alan G. Wood , Sidney B. Rigg , James M. Wark , Kyle K. Kirby
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/13009 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/17181 , H01L2924/09701
摘要： Methods for forming conductive vias include forming one or more via holes in a substrate. The via holes may be formed with a single mask, with protective layers, bond pads, or other features of the substrate acting as hard masks in the event that a photomask is removed during etching processes. The via holes may be configured to facilitate adhesion of a dielectric coating that includes a low-K dielectric material to the surfaces thereof. A barrier layer may be formed over surfaces of each via hole. A base layer, which may comprise a seed material, may be formed to facilitate the subsequent, selective deposition of conductive material over the surfaces of the via hole. The resulting semiconductor devices, intermediate structures, and assemblies and electronic devices that include the semiconductor devices that result from these methods are also disclosed.
摘要翻译：用于形成导电通孔的方法包括在衬底中形成一个或多个通孔。通孔可以形成有单个掩模，其中在蚀刻过程中去除光掩模的情况下，衬底的保护层，接合焊盘或其它特征用作硬掩模。通孔可以被配置为便于将包括低K电介质材料的电介质涂层粘附到其表面上。可以在每个通孔的表面上形成阻挡层。可以形成可以包括种子材料的基层，以便于导电材料随后的选择性沉积在通孔的表面上。还公开了包括由这些方法产生的半导体器件的所得半导体器件，中间结构和组件以及电子器件。

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