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71. 发明授权

US08064277B2 Control circuit of read operation for semiconductor memory apparatus 有权
标题翻译：半导体存储装置读操作的控制电路
公开(公告)号：US08064277B2
公开(公告)日：2011-11-22
申请号：US12493647
申请日：2009-06-29
申请人： Kwi Dong Kim
发明人： Kwi Dong Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C7/22 , G11C7/222
摘要： A control circuit for a read operation of a SERDES (SERializer and DESeriallizer) type semiconductor memory apparatus is disclosed that includes a first delay unit that is configured to generate and output a first delay signal to a first global input/output line driver by receiving a sensing-enable signal ‘IOSTB’, and to generate and output a second delay signal to a second global input/output line driver by receiving the sensing-enable signal. The first delay unit generates the second delay signal by delaying the sensing-enable signal in synchronization with a clock. The semiconductor memory apparatus also includes a second delay unit configured to generate a pipe latch control signal in response to the first delay signal and the second delay signal.
摘要翻译：公开了一种用于SERDES（串行器和解调器）型半导体存储装置的读取操作的控制电路，其包括第一延迟单元，其被配置为通过接收第一延迟单元生成第一延迟信号并将其输出到第一全局输入/ 感测使能信号“IOSTB”，并且通过接收感测使能信号来产生并将第二延迟信号输出到第二全局输入/输出线路驱动器。第一延迟单元通过与时钟同步地延迟感测使能信号来产生第二延迟信号。半导体存储装置还包括第二延迟单元，其被配置为响应于第一延迟信号和第二延迟信号产生管锁存控制信号。

72. 发明授权

US08040156B2 Lock detection circuit and lock detecting method 有权
标题翻译：锁定检测电路及锁定检测方法
公开(公告)号：US08040156B2
公开(公告)日：2011-10-18
申请号：US12466283
申请日：2009-05-14
申请人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon
发明人： Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon
IPC分类号： H03K5/19
CPC分类号： H03L7/095
摘要： Provided are a lock detection circuit and a lock detecting method. The lock detection circuit includes two delay devices, four flip-flops and two logic gates, and can accurately detect a lock state of a phase locked loop (PLL) circuit. Therefore, the lock detection circuit can be implemented in a simple structure, and as a result, the lock detection circuit can be compact in size and can consume less electric power. Also, the lock detecting method enables lock detection process to be simpler, so that a lock state can be detected within a short time period.
摘要翻译：提供锁定检测电路和锁定检测方法。锁定检测电路包括两个延迟器件，四个触发器和两个逻辑门，并且可以精确地检测锁相环（PLL）电路的锁定状态。因此，可以以简单的结构实现锁定检测电路，结果，锁定检测电路的尺寸可以小巧，并且可以消耗更少的电力。此外，锁定检测方法使得锁定检测处理更简单，从而可以在短时间内检测锁定状态。

73. 发明授权

US07978553B2 Apparatus for controlling I/O strobe signal in semiconductor memory apparatus 失效
标题翻译：用于在半导体存储装置中控制I / O选通信号的装置
公开(公告)号：US07978553B2
公开(公告)日：2011-07-12
申请号：US12493354
申请日：2009-06-29
申请人： Kwi Dong Kim
发明人： Kwi Dong Kim
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/18
摘要： A sensing enable signal control circuit determines a driving timing of an I/O sense amplifier based on a read-out result of data, which is stored in a dummy cell of a semiconductor memory apparatus. The sensing enable signal control circuit in a semiconductor memory apparatus includes a detection code generating unit configured to output a detection code according to a voltage level of dummy cell data, which are read out from a dummy cell through at least one read operation, in response to a column select enable signal, and a multiplexer configured to receive the detection code and a default code and output a delay code to delay a sensing enable signal.
摘要翻译：感测使能信号控制电路基于存储在半导体存储装置的虚拟单元中的数据的读出结果来确定I / O读出放大器的驱动定时。半导体存储装置中的感测使能信号控制电路包括：检测码生成单元，被配置为根据虚拟小区数据的电压电平输出检测码，所述虚拟小区数据通过至少一个读取操作从虚拟小区读出;响应以及多路复用器，被配置为接收检测码和默认码，并输出延迟码以延迟感测使能信号。

74. 发明申请

US20110148485A1 PHASE-LOCKED LOOP CIRCUIT COMPRISING VOLTAGE-CONTROLLED OSCILLATOR HAVING VARIABLE GAIN 失效
标题翻译：包含具有可变增益的电压控制振荡器的相位锁定环路
公开(公告)号：US20110148485A1
公开(公告)日：2011-06-23
申请号：US12882132
申请日：2010-09-14
申请人： Sang Hyun CHO , Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Seung Tak Ryu
发明人： Sang Hyun CHO , Hui Dong Lee , Kwi Dong Kim , Jong Kee Kwon , Seung Tak Ryu
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/099 , H03L2207/06
摘要： A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.
摘要翻译：提供了包括具有可变增益的压控振荡器（VCO）的锁相环（PLL）电路。相位频率检测器（PFD）检测参考信号和PLL反馈信号之间的相位差。电荷泵和环路滤波器依次处理PFD的输出信号。根据模式转换，VCO具有不同的增益。根据模式转换，从环路滤波器的输出信号和附加控制信号中选择施加到VCO的控制电压。

75. 发明申请

US20110103163A1 MULTI-BIT TEST CONTROL CIRCUIT 有权
标题翻译：多位测试控制电路
公开(公告)号：US20110103163A1
公开(公告)日：2011-05-05
申请号：US12792444
申请日：2010-06-02
申请人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
发明人： Kwi-Dong Kim , Mun-Phil Park , Sung-Ho Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/26 , G11C2029/2602
摘要： A multi-bit test control circuit includes an operation unit, a delay unit, and a generation unit. The operation unit is configured to combine a single source signal inputted to each bank with a delay signal generated by delaying the source signal by a certain time to generate a first pulse signal. The delay unit is configured to delay the first pulse signal by a certain time. The generation unit is configured to combine an output signal of the operation unit with an output signal of the delay unit to generate a second pulse signal for a bank interleaving multi-bit test.
摘要翻译：多位测试控制电路包括操作单元，延迟单元和生成单元。操作单元被配置为将输入到每个存储体的单个源信号与通过将源信号延迟一定时间而产生的延迟信号组合以产生第一脉冲信号。延迟单元被配置为将第一脉冲信号延迟一定时间。生成单元被配置为将操作单元的输出信号与延迟单元的输出信号组合，以产生用于存储体交叉多位测试的第二脉冲信号。

76. 发明申请

US20100246296A1 Write Driver and Semiconductor Memory Device Using the Same 有权
标题翻译：使用相同的驱动器和半导体存储器件
公开(公告)号：US20100246296A1
公开(公告)日：2010-09-30
申请号：US12487181
申请日：2009-06-18
申请人： Mun-Phil Park , Kwi-Dong Kim , Sung-Ho Kim
发明人： Mun-Phil Park , Kwi-Dong Kim , Sung-Ho Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/1078 , G11C7/1096 , G11C8/08
摘要： A semiconductor memory device includes a first memory bank and a second memory bank and a common write driver configured to drive write data to an activated memory bank of the first memory bank and the second memory bank. The common write driver of the semiconductor memory device includes a common write control block configured to generate common drive control signals corresponding to write data, and a common write drive block configured to drive transmission lines of a first memory bank or transmission lines of a second memory bank that are selected by a bank selection signal in response to the common drive control signals.
摘要翻译：半导体存储器件包括第一存储器组和第二存储器组以及公共写入驱动器，其被配置为将写入数据驱动到第一存储器组和第二存储器组的激活存储器组。半导体存储器件的公共写入驱动器包括：公共写入控制块，被配置为产生与写入数据相对应的公共驱动控制信号;以及公共写入驱动块，被配置为驱动第一存储体的传输线或第二存储器的传输线存储体，其响应于公共驱动控制信号由存储体选择信号选择。

77. 发明授权

US07663403B2 High-speed asynchronous digital signal level conversion circuit 失效
标题翻译：高速异步数字信号电平转换电路
公开(公告)号：US07663403B2
公开(公告)日：2010-02-16
申请号：US11943031
申请日：2007-11-20
申请人： Min Hyung Cho , Kwi Dong Kim , Chong Ki Kwon
发明人： Min Hyung Cho , Kwi Dong Kim , Chong Ki Kwon
IPC分类号： H03K19/0175
CPC分类号： H03K19/018528 , H03K19/0948
摘要： Provided is a high-speed asynchronous digital signal level conversion circuit converting an input signal of a first voltage level into a signal of a second voltage level. The conversion circuit is able to operate at high speed by connecting first and second nodes, at which the input signal of the first voltage level is converted to the signal of the second voltage level, to a second power source voltage of the second voltage level for fast voltage level conversion when the voltage level of the input signal is changed.
摘要翻译：提供了将第一电压电平的输入信号转换为第二电压电平的信号的高速异步数字信号电平转换电路。转换电路能够通过将第一和第二节点（第一电压电平的输入信号被转换为第二电压电平的信号）连接到第二电压电平的第二电源电压，当输入信号的电压电平改变时，进行快速电压电平转换。

78. 发明授权

US07576961B2 Electrostatic discharge protection circuit using triple welled silicon controlled rectifier 有权
标题翻译：静电放电保护电路采用三芯硅控整流器
公开(公告)号：US07576961B2
公开(公告)日：2009-08-18
申请号：US12018317
申请日：2008-01-23
申请人： Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
发明人： Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
IPC分类号： H02H9/00 , H01L23/62
CPC分类号： H01L29/7436 , H01L29/749 , H01L29/87 , H01L2924/0002 , H01L2924/00
摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.
摘要翻译：提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。因此，SCR的触发电压降低。此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。因此，ESD保护电路可以具有更大的放电容量。

79. 发明授权

US07545301B2 Multi-bit delta-sigma modulator 有权
标题翻译：多位delta-Σ调制器
公开(公告)号：US07545301B2
公开(公告)日：2009-06-09
申请号：US11950481
申请日：2007-12-05
申请人： Yi Gyeong Kim , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
发明人： Yi Gyeong Kim , Kwi Dong Kim , Chong Ki Kwon , Jong Dae Kim
IPC分类号： H03M3/00
CPC分类号： H03M3/374 , H03M3/338 , H03M3/424 , H03M3/45 , H03M3/452 , H03M3/454
摘要： A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.
摘要翻译：一种Δ-Σ调制器，具有用于积分输入信号的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 延迟电路，用于延迟模数转换器的输出信号; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。更具体地，Δ-Σ调制器具有适合于多位快速操作的低失真特性，其中通过延迟电路和差分延迟电路将反馈信号延迟一个时钟周期。

80. 发明授权

US07482966B2 Algorithm analog-to-digital converter 有权
标题翻译：算法模数转换器
公开(公告)号：US07482966B2
公开(公告)日：2009-01-27
申请号：US11946583
申请日：2007-11-28
申请人： Seung Chul Lee , Young Deuk Jeon , Kwi Dong Kim , Jong Kee Kwon
发明人： Seung Chul Lee , Young Deuk Jeon , Kwi Dong Kim , Jong Kee Kwon
IPC分类号： H03M1/38
CPC分类号： H03M1/0678 , H03M1/162
摘要： Provided is an algorithm analog-to-digital converter (ADC). The algorithm ADC obtains two digital outputs through different capacitor connections for one analog input signal and adds the digital output signals to obtain a final output value, so that a mismatch factor of the capacitor is removed to minimize a linearity limitation resulting from the capacitor mismatch. In addition, the algorithm ADC minimizes power consumption by making the operating frequency slow at a cycle requiring a high resolution and making the operating frequency fast at a cycle requiring a low resolution, i.e., outputting different operating clock frequencies according to a required resolution.
摘要翻译：提供了一种算法模数转换器（ADC）。算法ADC通过不同的电容器连接获得两个数字输出，用于一个模拟输入信号，并将数字输出信号相加以获得最终输出值，从而消除电容器的失配因子，以最小化由电容器失配引起的线性限制。此外，算法ADC通过使工作频率在需要高分辨率的周期中变慢，并使工作频率在需要低分辨率的周期（即，根据所需分辨率输出不同的工作时钟频率）的情况下将功率消耗最小化。

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